zl30110 Zarlink Semiconductor, zl30110 Datasheet - Page 12

• Manufacturer Part Number: zl30110
• Description: Telecom Rate Conversion Dpll
• Manufacturer: Zarlink Semiconductor

6.0
This section contains ZL30110 application specific details for power supply decoupling, reset operation, clock and
crystal operation.
6.1
Jitter levels on the ZL30110 output clocks may increase if the device is exposed to excessive noise on its power
pins. For optimal jitter performance, the ZL30110 device should be isolated from noise on power planes connected
to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note
ZLAN-178.
6.2
The ZL30110 can use either a clock or crystal as the master timing source.
6.2.1
When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency,
frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.
The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30110, and the OSCo
output should be left open as shown in Figure 5.
Power Supply Decoupling
Master Clock
Applications
Clock Oscillator
1
2
3
4
Frequency
Tolerance
Rise & fall time
Duty cycle
ZL30110
Table 1 - Clock Oscillator Specification
Figure 5 - Clock Oscillator Circuit
Zarlink Semiconductor Inc.
OSCo
OSCi
No Connection
ZL30110
25 MHz
as required (better than +/-50ppm)
< 8 ns
40% to 60%
12
25 MHz OUT
+3.3 V
+3.3 V
GND
0.1 µF
Data Sheet