zl30112 Zarlink Semiconductor, zl30112 Datasheet
zl30112
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zl30112 Summary of contents
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... The ZL30112 SLIC/CODEC DPLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices. The ZL30112 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable ...
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... Physical Description 1.1 Pin Connections AGND F8ko REF Figure 2 - Pin Connections (32 pin QFN) ZL30112 ZL30112 (E-pad Zarlink Semiconductor Inc. Data Sheet GND OSCi OSCo RST IC ...
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... C2o O Clock 2.048 MHz (LVCMOS). This is a 2.048 MHz clock output. 25 AGND Analog Ground. 0V. 26 F8ko O Frame Pulse (LVCMOS). This kHz frame pulse which marks the beginning of a 125 us frame. Pulse width is 122 ns. ZL30112 Description nominal. DC nominal. DC nominal. DC nominal. DC nominal. ...
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... Internal Connection. Connect to VDD Internal Connection. Connect to VDD Positive Analog Supply Voltage. +3 Internal Connection. Connect to GND. 33 GND Ground Package E-pad. This pin is internally connected to device GND. It must be externally connected to GND. ZL30112 Description nominal Zarlink Semiconductor Inc. Data Sheet ...
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... Functional Description The ZL30112 is a SLIC/CODEC DPLL providing timing (clock) and synchronization (frame) signals to network interface cards. Figure functional block diagram which is described in the following sections. 3.1 Reference Monitor The input reference is monitored by two reference monitor blocks. The block diagram of reference monitoring is shown in Figure 3. The reference frequency is detected and the clock is continuously monitored for two independent criteria that indicate abnormal behavior of the reference signal, for example ...
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... Digital Phase Lock Loop (DPLL) The DPLL of the ZL30112 consists of a phase detector, an integrated on-chip loop filter, and a digitally controlled oscillator as shown in Figure 4. The data path from the phase detector to the filter is tapped and routed to the lock indicator that provides a lock indication which is output at the LOCK pin. ...
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... The clock and frame pulse outputs have limited drive capability and should be buffered when driving high capacitance loads. 3.5 Master Clock The ZL30112 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. ZL30112 7 Zarlink Semiconductor Inc ...
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... Automatic Freerun Mode Automatic freerun mode is typically used for short durations while system synchronization is temporarily disrupted. In Automatic freerun mode, the ZL30112 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on the freerun accuracy of the external oscillator. ...
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... Freerun Accuracy Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the ZL30112, the Freerun accuracy is equal to the master clock (OSCi) accuracy. 5.5 Capture Range Also referred to as pull-in range ...
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... Power Supply Decoupling Jitter levels on the ZL30112 output clocks may increase if the device is exposed to excessive noise on its power pins. For optimal jitter performance, the ZL30112 device should be isolated from noise on power planes connected to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note ZLAN-178 ...
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... The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30112 and the OSCo output should be left open as shown in Figure 6. 6.2.2 Crystal Oscillator Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made crystal, resistor and capacitors is shown in Figure 7. The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. ...
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... The 100 Ω resistor and the 1 µH inductor may improve stability and are optional. 6.3 Power Up Sequence The ZL30112 requires that the 3 not powered after the 1.8 V. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are given: 1. Power-up 3.3 V first, 1.8 V later 2 ...
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... Voltages are with respect to ground (GND) unless otherwise stated. DC Electrical Characteristics* Characteristics 1 Supply current with: OSCi = Core supply current with: OSCi = Schmitt trigger Low to High threshold point 6 Schmitt trigger High to Low threshold point 7 Input leakage current ZL30112 Symbol V DD_R V CORE_R V PIN V OSC I PIN ESD Sym ...
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... Rise and Fall Threshold Voltage Low * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. ALL SIGNALS t t IRF, ORF Figure 9 - Timing Parameter Measurement Voltage Levels. ZL30112 Sym. Min. Max 0.4 OL Sym ...
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... Output clock and frame pulse rise time 7 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions and 30 pF load. F8o C2o C8o Figure 10 - Output Timing Referenced to F8o ZL30112 Symbol Min. t 120 REF8kP t 263 REF2P t ...
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... REF F8ko AC Electrical Characteristics* - OSCi 20 MHz Master Clock Input Characteristics 1 Oscillator Tolerance 2 Duty cycle 3 Rise time 4 Fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30112 Symbol t REF8kD t REF2_F8kD t REF8_F8kD t REF19_F8kD t t REFW REFW t REF< ...
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... Lock Time represent time to achieve phase/frequency lock and it excludes time to pull-in the input to output phase difference. Performance Characteristics* - Unfiltered Intrinsic Jitter Signal 1 C2o 2 C8o 3 F8ko (8 kHz) * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30112 Min. Typ. Max. Units NA ppm -130 +130 ppm ...
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... Zarlink Semiconductor 2003 All rights reserved ISSUE 3 ACN CDCA CDCA CDCA 30-01-2004 15-08-2005 DATE 22-08-2005 APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...