zl30112 Zarlink Semiconductor, zl30112 Datasheet - Page 6

• Manufacturer Part Number: zl30112
• Description: Slic/codec Dpll
• Manufacturer: Zarlink Semiconductor

3.2
The TIE Corrector Circuit eliminates phase transients on the output clock that may occur in the course of recovery
from Automatic Freerun mode to Normal mode.
On recovery from Automatic Freerun mode, the TIE corrector circuit measures the phase delay between the current
phase (feedback signal) and the phase of the selected reference signal. This delay value is stored in the TIE
corrector circuit. This circuit creates a new virtual reference signal that is at the same phase position as the
feedback signal. By using the virtual reference, the PLL minimizes the phase transient it experiences when it
switches to another reference input or recovers from Automatic Freerun mode.
3.3
The DPLL of the ZL30112 consists of a phase detector, an integrated on-chip loop filter, and a digitally controlled
oscillator as shown in Figure 4. The data path from the phase detector to the filter is tapped and routed to the lock
indicator that provides a lock indication which is output at the LOCK pin.
Phase Detector - the phase detector compares the virtual reference signal from the TIE corrector circuit with the
feedback signal and provides an error signal corresponding to the phase difference between the two. This error
signal is passed to the loop filter circuit.
Loop Filter - the loop filter is similar to a first order low pass filter with bandwidth of 29 Hz suitable to provide timing
and synchronization for network interface cards.
Time Interval Error (TIE) Corrector Circuit
Digital Phase Lock Loop (DPLL)
TIE corrector circuit
virtual reference
from
detector
phase
Figure 4 - DPLL Block Diagram
Zarlink Semiconductor Inc.
control state machine
ZL30112
state select from
loop filter
6
controlled
oscillator
indicator
digitally
lock
feedback signal from
frequency select MUX
LOCK
frequency synthesizer
DPLL reference to
Data Sheet