zl30136 Zarlink Semiconductor, zl30136 Datasheet - Page 3

• Manufacturer Part Number: zl30136
• Description: Gbe And Telecom Rate Network Interface Synchronizer
• Manufacturer: Zarlink Semiconductor

Pin Description
Input Reference
Output Clocks and Frame Pulses
Control
Status
Serial Interface (SPI/I
Pin #
G8
G7
G5
B1
A3
B4
A1
A2
A4
D8
B2
E1
H1
C1
eth_clk
sck/scl
Name
sync0
sync1
sync2
mode
p_clk
rst_b
p_fp
hold
ref0
ref1
ref2
lock
2
C)
Type
I/O
I/B
I
I
O
O
O
I
O
O
I
u
u
u
Input References 2:0 (LVCMOS, Schmitt Trigger). These input references are
available to the DPLL for synchronizing output clocks. All three input references
can lock to 2 kHz or any multiple of 8 kHz up to 77.76 MHz including 25 MHz and
50 MHz. Input ref0 and ref1 have additional configurable pre-dividers allowing
input frequencies of 62.5 MHz, 125 MHz, and 155.52 MHz. These pins are
internally pulled up to V
Frame Pulse Synchronization References 2:0 (LVCMOS, Schmitt Trigger).
These are optional frame pulse synchronization inputs associated with input
references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%
duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.
These pins are internally pulled up to V
Network Output Clock (LVCMOS). This output can be configured to provide
any of the Ethernet clock rates: 12.5 MHz, 25 MHz, 50 MHz, 62.5 MHz, or
125 MHz.
Programmable Telecom Synthesizer - Output Clock (LVCMOS). This output
can be configured to provide telecom clock rates in multiples of 8 kHz up to
77.76 MHz. The default frequency for this output is 2.048 MHz.
Programmable Telecom Synthesizer - Output Frame Pulse (LVCMOS). This
output can be configured to provide virtually any style of output frame pulse. The
default frequency for this frame pulse output is 8 kHz.
Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To
ensure proper operation, the device must be reset after power-up. Reset should
be asserted for a minimum of 300 ns.
DPLL Mode Select (LVCMOS, Schmitt Trigger). During reset, the level on this
pin determines the default mode of operation for DPLL (Normal=0 or Freerun=1).
After reset, the mode of operation can be controlled directly with this pin, or by
accessing the dpll_modesel register (0x1F) through the serial interface. This pin
is internally pulled up to Vdd.
Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL. This output
goes high when the DPLL’s output is frequency and phase locked to the input
reference.
Holdover Indicator (LVCMOS). This pin goes high when the DPLL enters the
holdover mode.
Clock for Serial Interface (LVCMOS). Serial interface clock. When i2c_en = 0,
this pin acts as the sck pin for the serial interface. When i2c_en = 1, this pin acts
as the scl pin (bidirectional) for the I
Zarlink Semiconductor Inc.
ZL30136
3
dd
.
Description
2
C interface.
dd.
Short Form Data Sheet