zl30138 Zarlink Semiconductor, zl30138 Datasheet - Page 2

• Manufacturer Part Number: zl30138
• Description: Oc-192/stm-64 Sonet/sdh/10gbe Stratum 2/3/3e System Synchronizer/sets
• Manufacturer: Zarlink Semiconductor

Pin Description
Input Reference
Output Clocks and Frame Pulses
Pin #
D10
G10
B10
A10
C1
B2
A3
C3
B3
B4
C4
A4
B1
A1
A2
C5
B5
A9
B9
sync8/ext_fb_fp
ref8/ext_fb_clk
apll_clk0
apll_clk1
diff0_p
diff0_n
diff1_p
diff1_n
Name
sync0
sync1
sync2
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
Type
I/O
O
O
O
O
I
I
I
I
u
u
u
u
Input References 7:0 (LVCMOS, Schmitt Trigger). These input references are
available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight
input references can lock to any multiple of 8 kHz up to 77.76 MHz including
25 MHz and 50 MHz. Input ref0 and ref1 have additional configurable pre-
dividers allowing input frequencies of 62.5 MHz, 125 MHz, and 155.52 MHz.
These pins are internally pulled up to V
Frame Pulse Synchronization References 2:0 (LVCMOS, Schmitt Trigger).
These are optional frame pulse synchronization inputs associated with input
references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%
duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.
These pins are internally pulled up to V
Input Reference 8/External DPLL Feedback Clock (LVCMOS, Schmitt
Trigger). This pin acts as either an ext_fb_clk input or as the ref8 input. The
desired function for the pin is selectable through the software interface with a
programmable register bit. This pin is internally pulled up to V
when not in use.
Frame Pulse Synchronization Reference 8/External DPLL Feedback Frame
Pulse (LVCMOS, Schmitt Trigger). This pin acts as either an ext_fb_fp input or
as the sync8 input. The desired function for the pin is selectable through the
software interface with a programmable register bit. This pin is internally pulled
up to V
Differential Output Clock 0 (LVPECL). When in SONET/SDH mode, this output
can be configured to provide any one of the available SONET/SDH clocks
(6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz). When in Ethernet mode, this output can be
configured to provide any of the Ethernet clocks (25 MHz, 50 MHz, 62.5 MHz,
125 MHz, 156.25 MHz, 312.5 MHz). See “Output Clocks and Frame Pulses” on
page 31 for more details on clock frequency settings.
Differential Output Clock 1 (LVPECL). When in SONET/SDH mode, this output
can be configured to provide any one of the available SONET/SDH clocks
(6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz). When in Ethernet mode, this output can be
configured to provide any of the Ethernet clocks (25 MHz, 50 MHz, 62.5 MHz,
125 MHz, 156.25 MHz, 312.5 MHz). See “Output Clocks and Frame Pulses” on
page 31 for more details on clock frequency settings.
APLL Output Clock 0 (LVCMOS). This output can be configured to provide any
one of the SONET/SDH clock outputs up to 77.76 MHz or any of the Ethernet
clock rates up to 125 MHz. The default frequency for this output is 77.76 MHz.
APLL Output Clock 1 (LVCMOS). This output can be configured to provide any
one of the SONET/SDH clock outputs up to 77.76 MHz or any of the Ethernet
clock rates up to 125 MHz. The default frequency for this output is 19.44 MHz.
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Leave open when not in use.
Zarlink Semiconductor Inc.
ZL30138
5
Description
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Short Form Data Sheet
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