zl30138 Zarlink Semiconductor, zl30138 Datasheet - Page 3

• Manufacturer Part Number: zl30138
• Description: Oc-192/stm-64 Sonet/sdh/10gbe Stratum 2/3/3e System Synchronizer/sets
• Manufacturer: Zarlink Semiconductor

Control
Pin #
H10
E10
F10
K10
J10
K9
K7
K8
E1
H5
J7
J5
dpll1_hs_en
dpll2_ref
apll_fp0
apll_fp1
p0_clk0
p0_clk1
p1_clk0
p1_clk1
p0_fp0
p0_fp1
Name
fb_clk
rst_b
Type
I/O
O
O
O
O
O
O
O
O
O
O
I
I
u
APLL Output Frame Pulse 0 (LVCMOS). This output can be configured to
provide virtually any style of output frame pulse synchronized with an associated
SONET/SDH family output clock. The default frequency for this frame pulse
output is 8 kHz.
APLL Output Frame Pulse 1 (LVCMOS). This output can be configured to
provide virtually any style of output frame pulse synchronized with an associated
SONET/SDH family output clock. The default frequency for this frame pulse
output is 2 kHz.
Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 2.048 MHz.
Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p0_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 8.192 MHz.
Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz.
Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz
Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1).
Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p1_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 3.088 MHz (2x DS1).
Feedback Clock (LVCMOS). This output is a buffered copy of the feedback
clock for DPLL1. The frequency of this output always equals the frequency of the
selected reference.
DPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the
output of the reference selector for DPLL2. Switching between input reference
clocks at this output is not hitless.
Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To
ensure proper operation, the device must be reset after power-up. Reset should
be asserted for a minimum of 300 ns.
DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at
this input enables hitless reference switching. A logic low disables hitless
reference switching and re-aligns DPLL1’s output phase to the phase of the
selected reference input. This feature can also be controlled through software
registers. This pin is internally pulled up to Vdd.
Zarlink Semiconductor Inc.
ZL30138
6
Description
Short Form Data Sheet