m21120 Mindspeed Technologies, m21120 Datasheet - Page 12

• Manufacturer Part Number: m21120
• Description: M21120 Crosspoint Switch Data Sheet
• Manufacturer: Mindspeed Technologies

21120-DSH-001-B, 3/27/03
Serial Interface and Switch Programming
Introduction
The crosspoint switch uses +2.5 or 3.3 V CMOS interface levels to program the Switch State (SS). All control inputs have a 50 kΩ
internal pull-up except for xInDis and xOutDis, which have internal pull-downs. The communication protocol may be either a serial
synchronous interface or an 8-bit parallel asynchronous interface. Either interface can:
This section details the operation of the I/O interface and switch programming. The auxiliary functions and address mapping are
explained in the section, Switch Function Details.
The various switch functions are controlled by 8-bit registers that are addressed by the 8-bit address (ADDR) bus. The register
contents are transferred via the 8-bit data (DATA) bus during a READ or WRITE.
The Switch State of the crosspoint switch uses a double buffered register. The Active Configuration Latch (ACL) holds the current
switch setting while the Input Configuration Latch (ICL) holds either the current switch setting or the next switch setting, depending on
the mode of operation.
The xSET Mode register (ADDR=E7h) selects the two modes of operation. DATA=00h enables Mode 1, which is the default mode
after a reset. In Mode 1, the switch state changes with each WRITE to the register that determines the SS. In the WRITE mode, as
xDS goes low, the input channel specified by DATA for the output selected by ADDR passes directly through the double buffer (ICL/
ACL), which routes the selected input to the newly selected output channel. On the rising edge of xDS, ICL and ACL both store (latch)
this SS.
In Mode 2, the SS is written first to the ICL and the switch state does not change. With either the hardware or software xSET
command, the contents of the ICL transfer to the ACL, changing the SS. This mode allows 1 to 68 channels to change simultaneously.
The hardware xSET mode is enabled by DATA=10b written into xSET Mode (ADDR=E7h). On the falling edge of xSet, the contents of
the ICL pass to the ACL, changing the SS. On the rising edge of xSet, the SS is latched.
write operation.
operations.
To enable the software xSet mode, where the xSet command is sent via a software command rather than a hardware command, a
value of 01h should be written into the xSET Mode register (address E7h). Once in the software xSet mode, an xSet command can be
issued with a write of any value to the software xSET register (address E8h). A write of any value to the software xSET register
(address E8h) will update the ACL with the current ICL contents and change the switch state.
Register Concept
Switch State Register Concept
1. Program the switch state
2. Individually enable/disable inputs/outputs
3. Access control registers and auxiliary functions
4. Read back the current state of the switch
Figure 3
Table 11
Figure 4
represents a timing diagram for the Parallel I/O, Mode 1.
defines the timing specifications for parallel read operations.
illustrates the timing for a parallel read operation.
34 x 34 3.2 Gbps Crosspoint Switch with Input Equalization
Mindspeed Technologies™
Table 10
defines the timing specifications for parallel write
Figure 3
illustrates the timing for a parallel
M21120
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