mt9085bpr1 Zarlink Semiconductor, mt9085bpr1 Datasheet - Page 4

• Manufacturer Part Number: mt9085bpr1
• Description: Pac - Parallel Access Circuit
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Pin #
47
48
49
50
51
52
53
54
55
56
57
58
59
Name
CFPo
DFPo
DFPo
MCB
C16i
V
C4o
C2o
F0o
V
V
F0i
NC
DD
SS
SS
Connect Memory Frame Pulse (Output). Framing signal with a nominal 8 kHz frequency; goes low
71 (CKD=0) or 68 (CKD=1) C16 clock cycles before the frame boundary established by F0i. The
signal is used by the connection memory in a typical 1 k or 2 k switch configuration. See Figure 15 for
timing information.
Data Memory Frame Pulse (Output). Framing signal with nominal 4 kHz frequency; changes state 64
(CKD=0) or 65 (CKD=1) C16 clock cycles after the frame boundary established by F0i. This signal is a
complement of DFPo. See Figure 15 for timing information. The signal is used by SMXs (MT9080s)
making up the Data Memory in a typical 1 k or 2 k switch configuration.
Framing Type 0 Signal (Output). 8 kHz framing signal output by the PAC to indicate the frame
boundary synchronized to C16. This framing signal is aligned with C4o and is output by the PAC for use
by other devices in a typical switch configuration. Refer to Figures 4 and 5 for functional timing
information.
Framing Type 0 Signal (TTL compatible input). This input signal establishes the frame boundary for
the serial input/output streams. The first falling edge of C4i following the falling edge of F0i establishes
the frame boundaries. Refer to Figure 13 for timing information.
16 MHz Clock Input. The 16.384 MHz clock signal input at this pin must be phase-locked to the 4.096
MHz clock input at C4i. See Figure 13 for timing information.
Ground.
Supply Input. +5 V
Data Memory Frame Pulse (Output). 4 kHz framing signal; changes state 64 (CKD=0) or 65
(CKD=1) C16 clock cycles after the frame boundary established by F0i. This signal is a complement of
DFPo. See Figure 15. The signal is used by SMXs (MT9080s) making up the Data Memory in a typical
2 k switch configuration.
4.096 MHz Clock Output. This is a 4.096 MHz clock signal derived from the 16 MHz master clock
input at C16. The falling edge of C4o occurs in the middle of the regenerated frame pulse output at F0o.
Refer to Figures 4 and 5 for functional timing information.
2.048 MHz Clock Output. This is a 2.048 MHz clock signal derived from the 16 MHz master clock
input. The rising edge of this clock signal occurs in the middle of the regenerated frame pulse output at
F0o. Refer to Figures 4 and 5 for functional timing information.
No Connection.
Ground.
Mode Control-B (Input). This control input performs two different functions, depending on the state of
MCA pin.
In parallel to serial mode (MCA=1), MCB defines which clock edge latches in the data.
MCB=0
MCB=1
In serial to parallel mode (MCA=0), the MCB pin controls the state of the parallel bus driver as follows:
MCB=0
MCB=1
Data on the parallel bus is latched into the device with the every second falling edge of
C16. See Figure 6.
The output drivers are enabled for only half the timeslot. The data is clocked out on the
Data on the parallel bus is latched into the device with every alternate positive clock
The parallel data bus output drivers are enabled for the duration of the channel timeslot
edge.
first falling edge within the timeslot and disabled on the next falling edge. See Figure 7.
(two C16 Clock Periods). The data is clocked out on the first positive edge within a
timeslot and disabled on the last edge.
Zarlink Semiconductor Inc.
MT9085B
4
Description
Data Sheet