zl50058 Zarlink Semiconductor, zl50058 Datasheet - Page 26

• Manufacturer Part Number: zl50058
• Description: 12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 48 Input And 48 Output Streams
• Manufacturer: Zarlink Semiconductor

ZL50057/8
Data Sheet
2.2
Frame Pulse Input and Master Input Clock Timing
The input frame pulse (FP8i) is an 8 kHz input signal active for 122 ns or 244 ns at the frame boundary. The FPW
bit in the Control Register must be set according to the applied pulse width. See Pin Description and Table 21,
“Control Register Bits” on page 64, for details.
The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 7,
ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates. The ZL50057/8 device will automatically
detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The
output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame
pulse. The active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL.
Note that the active edge of ST-BUS is falling edge, which is the default mode of the device, while GCI-Bus uses
rising edge as the active edge. Although GCI frame pulse will be automatically detected, to fully conform to
GCI-Bus operation, the device should be set to use C8i rising edge as the active edge (by setting bit C8IPOL HIGH)
when GCI-Bus is used.
For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS
frame pulse format with a single width frame pulse of 122 ns and a falling active clock-edge, unless explicitly stated
otherwise.
In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to
the output ports. The generated frame pulses (FP8o, FP16o) will be provided in the same format as the master
frame pulse (FP8i). The polarity of C8o and C16o, at the frame boundary, can be controlled by the Control Register
bit, COPOL. An analog phase lock loop (APLL) is used to multiply the input clock frequency on C8i to generate an
internal clock signal operating at 131.072 MHz.
26
Zarlink Semiconductor Inc.