zl50418 Zarlink Semiconductor, zl50418 Datasheet - Page 58
zl50418
Manufacturer Part Number
zl50418
Description
Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50418.pdf
(163 pages)
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ZL50418
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USER_
PORT”N”_LOW
USER_
PORT”N”_HIGH
USER_
PORT1:0_
PRIORITY
USER_
PORT3:2_
PRIORITY
USER_
PORT5:4_
PRIORITY
USER_
PORT7:6_PRI
ORITY
USER_PORT_
ENABLE
WLPP10
WLPP32
WLPP54
WLPP76
WLPE
RLOWL
RLOWH
RHIGHL
RHIGHH
RPRIORITY
CPUQOSC1~3
6. MISC Configuration Registers
MII_OP0
MII_OP1
FEN
Register
User Define Logical Port “N” Low
(N=0-7)
User Define Logical Port “N” High
User Define Logic Port 1 and 0
Priority
User Define Logic Port 3 and 2
Priority
User Define Logic Port 5 and 4
Priority
User Define Logic Port 7 and 6
Priority
User Define Logic Port Enable
Well known Logic Port Priority for
1 and 0
Well known Logic Port Priority for
3 and 2
Well known Logic Port Priority for
5 and 4
Well-known Logic Port Priority for
7 & 6
Well known Logic Port Enable
User Define Range Low Bit 7:0
User Define Range Low Bit 15:8
User Define Range High Bit 7:0
User Define Range High Bit 15:8
User Define Range Priority
Byte limit for TxQ on CPU port
MII Register Option 0
MII Register Option 1
Feature Registers
Description
Zarlink Semiconductor Inc.
ZL50418
58
580 + 2N
581 + 2N
590
591
592
593
595
596
597
598
599
59A
59B
59C
59D
59E
5A0-5A2
602
594
600
601
CPU Addr
(Hex)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0D6-0D
D
0DE-0E
5
0E6
0E7
0E8
0E9
0EA
0EB
0EC
0ED
0EE
0EF
0F4
0F5
0D3
0D4
0D5
NA
0F0
0F1
0F2
(Hex)
Addr
I
2
C
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
010
Default
Data Sheet
Notes
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