am79c981 Advanced Micro Devices, am79c981 Datasheet - Page 10

• Manufacturer Part Number: am79c981
• Description: Integrated Multiport Repeater Plus? Imr+? ??9
• Manufacturer: Advanced Micro Devices

The reconnection algorithm option (standard or alter-
nate) is a global function for the TP ports, i.e. all TP ports
use the same reconnection algorithm. The AUI
reconnection algorithm option is programmed inde-
pendently of the TP port reconnection option.
Link Test
The integral TP ports implement the Link Test function
as specified in the 802.3 10BASE-T standard. The IMR+
device will transmit Link Test pulses to any TP port after
that port’s transmitter has been inactive for more than 8
to 17 ms. Conversely, if a TP port does not receive any
data packets or Link Test pulses for more than 65 to
132 ms and the Link Test function is enabled for that
port then that port will enter link fail state. A port in link
fail state will be disabled by the IMR+ chip (repeater
transmit and receive functions disabled) until it receives
either four consecutive Link Test pulses or a data pack-
et. The Link Test receive function itself can be disabled
via the IMR+ chip management port on a port-by-port
basis to allow the IMR+ device to interoperate with pre-
10BASE-T twisted pair networks that do not implement
the Link Test function. This interoperability is possible
because the IMR+ device will not allow the TP port to en-
ter link fail state, even if no Link Test pulses or data
packets are being received. Note however that the
IMR+ chip will always transmit Link Test pulses to all TP
ports regardless of whether or not the port is enabled,
partitioned, in link fail state, or has its Link Test receive
function disabled.
Polarity Reversal
The TP ports have the optional (programmable) ability
to invert (correct) the polarity of the received data if the
TP port senses that the received data packet waveform
polarity is reversed due to a wiring error. This receive
circuitry polarity correction allows subsequent packets
1–80
*Only when used with the HIMIB device.
Active LOW outputs
Active HIGH outputs
SO Output
DAT, JAM
STR
Transmitters (TP and AUI)
Receivers (TP and AUI)
AUI Partitioning/Reconnection Algorithm
TP Port Partitioning/Reconnection Algorithm
Link Test Function for TP Ports
Automatic Receiver Polarity Reversal Function
AMD
Function
Table 1. IMR+ Chip After Reset
PRELIMINARY
HIGH
LOW
HIGH
HI-IMPEDANCE
LOW
IDLE
ENABLED
STANDARD ALGORITHM
STANDARD ALGORITHM
ENABLED, TP PORTS IN LINK FAIL
DISABLED
Am79C981
State After Reset
to be repeated with correct polarity. This function is exe-
cuted once following reset or link fail, and has a
programmable enable/disable option on a port-by-port
basis. This function is disabled upon reset and can be
enabled via the IMR+ chip Management Port.
Reset
The IMR+ device enters reset state when the RST pin is
driven LOW. After the initial application of power, the
RST pin must be held LOW for a minimum of 150 s
(3000 X1 clock cycles). If the RST pin is subsequently
asserted while power is maintained to the IMR+ device,
a reset duration of only 4 s is required. The IMR+ chip
continues to be in the reset state for 10 X1 clocks
(0.5 s) following the rising edge of RST. During reset,
the output signals are placed in their inactive states.
This means that all analog signals are placed in their idle
states, bidirectional signals (except STR signal) are not
driven, active LOW signals are driven HIGH, and all ac-
tive HIGH signals and the STR pin are driven LOW.
An internal circuit ensures that a minimum reset pulse is
generated for all internal circuits. For a RST input with a
slow rising edge, the input buffer threshold may be
crossed several times due to ripple on the input
waveform.
In a multiple IMR+ chip repeater the RST signal should
be applied simultaneously to all IMR+ devices and
should be synchronized to the external X1 clock. Reset
synchronization is also required when accessing the
PAM (Port Activity Monitor).
The SI signal should be held HIGH for at least 500 ns fol-
lowing the rising edge of RST.
Table 1 summarizes the state of the IMR+ chip following
reset.
Pull Up/Pull Down
Terminated
Pull Up*
Either
N/A
N/A
N/A
N/A
No
No
No
No