am79c981 Advanced Micro Devices, am79c981 Datasheet - Page 6

• Manufacturer Part Number: am79c981
• Description: Integrated Multiport Repeater Plus? Imr+? ??9
• Manufacturer: Advanced Micro Devices

1–76
PIN DESCRIPTION
ACK
Acknowledge
Input, Active LOW
When this input is asserted, it signals to the requesting
IMR+ device that it may control the DAT and JAM pins.
If the IMR+ chip is not requesting control of the DAT line
(REQ pin HIGH), then the assertion of the ACK signal
indicates the presence of valid collision status on the
JAM or valid data on the DAT line.
AV
Analog Power
Power Pin
These pins supply the +5 V to the RXD+/– receivers,
the DI+/– and CI+/– receivers, the DO+/– drivers, the
internal PLL, and the internal voltage reference of the
IMR+ device. These power pins should be decoupled
and kept separate from other power and ground
planes.
AV
Analog Ground
Ground Pin
These pins are the 0 V reference for AV
COL
Expansion Collision
Input, Active LOW
When this input is asserted by an external arbiter, it sig-
nifies that more than one IMR+ device is active and that
each IMR+ device should generate the Collision Jam
sequence independently.
CI+, CI–
Control In
Input
AUI port differential receiver. Signals comply with IEEE
802.3, Section 7.
CRS
Carrier Sense
Output
The states of the internal carrier sense signals for the
AUI port and the eight twisted-pair ports are serially
output on this pin continuously. The output serial bit
stream is synchronized to the X
DAT
Data
Input/Output/3-State
In non-collision conditions, the active IMR+ device will
drive DAT with NRZ data, including regenerated pre-
amble. During collision, when JAM = HIGH, DAT is
used to signal a multiport (DAT = 0) or single-port
(DAT = 1) condition.
DD
SS
1
clock.
DD
.
P R E L I M I N A R Y
Am79C981
When ACK is not asserted, DAT is in high impedance.
If REQ and ACK are both asserted, then DAT is an out-
put. If ACK is asserted and REQ not asserted, then
DAT is an input.
This pin needs to be either pulled up or pulled down
through a high-value resistor.
DI+, DI–
Data In
Input
AUI port differential receiver. Signals comply with IEEE
802.3, Section 7.
DO+, DO–
Data Out
Output
AUI port differential driver. Signals comply with IEEE
802.3, Section 7.
DV
Digital Power
Power Pin
These pins supply +5 V to the logic portions of the
IMR+ chip and the TXP+/–, TXD+/–, and DO+/– line
drivers.
DV
Digital Ground
Ground Pin
These pins are the 0 V reference for DV
JAM
Jam
Input/Output/3-State
When JAM is asserted, the state of DAT will indicate
either a multiport (DAT = 0) or single-port (DAT = 1) col-
lision condition.
When ACK is not asserted, JAM is in high impedance.
If REQ and ACK are both asserted, then JAM is an out-
put. If ACK is asserted and REQ not asserted, then
JAM is an input.
This pin needs to be either pulled up or pulled down
through a high-value resistor.
DV
DD
SS
43, 49
DD
19
28
59
68
Pin #
35, 37, 46, 51
DV
SS
16
31
56
71
Pin #
TP ports 0 & 1 drivers
TP ports 2 & 3 drivers
Core logic and expansion
and control pins
TP ports 4 & 5 drivers
TP ports 6 & 7 drivers
Function
DD
.