89hpes12t3bg2 Integrated Device Technology, 89hpes12t3bg2 Datasheet - Page 12

• Manufacturer Part Number: 89hpes12t3bg2
• Description: 12-lane 3-port Gen2 Pci Express Switch
• Manufacturer: Integrated Device Technology

© 2009 Integrated Device Technology, Inc
IDT 89HPES12T3BG2 Data Sheet
T
T
DATA
T
T
T
T
PCIe Receive
UI
T
T
MAX JITTER
T
T
T
T
T
TX-IDLE-SET-TO-IDLE
TX-IDLE-TO-DIFF-
TX-SKEW
MIN-PULSED
TX-HF-DJ-DD
RF-MISMATCH
RX-EYE (with jitter)
RX-EYE-MEDIUM TO
RX-SKEW
RX-HF-RMS
RX-HF-DJ-DD
RX-LF-RMS
RX-MIN-PULSE
1.
Parameter
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0
Maximum time to transition to a valid Idle after sending
an Idle ordered set
Maximum time to transition from valid idle to diff data
Transmitter data skew between any 2 lanes
Minimum Instantaneous Lone Pulse Width
Transmitter Deterministic Jitter > 1.5MHz Bandwidth
Rise/Fall Time Differential Mismatch
Unit Interval
Minimum Receiver Eye Width (jitter tolerance)
Max time between jitter median & max deviation
Lane to lane input skew
1.5 — 100 MHz RMS jitter (common clock)
Maximum tolerable DJ by the receiver (common clock)
10 KHz to 1.5 MHz RMS jitter (common clock)
Minimum receiver instantaneous eye width
GPIO
GPIO[11,7:0]
1.
they are asynchronous.
2.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
The values for this symbol were determined by calculation, not by testing.
Signal
Description
1
*Notice: The information in this document is subject to change without notice
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
Symbol
Table 11 GPIO AC Timing Characteristics
Tpw
2
Reference
Edge
None
12 of 30
Min
399.88
0.4
Min Max Unit
50
1
Gen 1
Typ
400
NA
NA
NA
NA
NA
NA
NA
—
1
Max
400.12
ns
1.3
0.3
20
8
8
1
Reference
Diagram
Timing
199.94
Min
0.9
0.4
0.6
1
Gen 2
Typ
1
Max
200.06
0.15
1.3
0.1
3.4
4.2
88
8
8
8
1
Units
July 1, 2009
ns
ns
ns
ps
ns
ps
ps
ps
UI
UI
UI
UI
UI
UI