89hpes48t12 Integrated Device Technology, 89hpes48t12 Datasheet
89hpes48t12
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89hpes48t12 Summary of contents
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... Device Overview The 89HPES48T12 is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES48T12 is a 48-lane, 12-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high-performance applications such as servers, storage, and communications/networking. It provides connectivity and ...
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... IDT 89HPES48T12 Data Sheet – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports optional PCI Express Advanced Error Reporting – Supports PCI Express Hot-Plug • Compatible with Hot-Plug I/O expanders used on PC motherboards – ...
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... IDT 89HPES48T12 Data Sheet As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES48T12 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES48T12 registers supports SMBus arbitration ...
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... IDT 89HPES48T12 Data Sheet Pin Description The following tables lists the functions of the pins provided on the PES48T12. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differ- ential signals end with a suffix “ ...
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... IDT 89HPES48T12 Data Sheet Signal PE7TP[3:0] PE7TN[3:0] PE8RP[3:0] PE8RN[3:0] PE8TP[3:0] PE8TN[3:0] PE9RP[3:0] PE9RN[3:0] PE9TP[3:0] PE9TN[3:0] PE10RP[3:0] PE10RN[3:0] PE10TP[3:0] PE10TN[3:0] PE11RP[3:0] PE11RN[3:0] PE11TP[3:0] PE11TN[3:0] REFCLKM REFCLKP[3:0] REFCLKN[3:0] Signal MSMBADDR[4:1] MSMBCLK MSMBDAT Type Name/Description O PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pairs for port 7 ...
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... IDT 89HPES48T12 Data Sheet Signal SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] Type Name/Description I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus ...
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... IDT 89HPES48T12 Data Sheet Signal GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GPIO[16] GPIO[17] GPIO[18] GPIO[19] GPIO[20] GPIO[21] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P5RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 5 I/O General Purpose I/O ...
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... IDT 89HPES48T12 Data Sheet Signal GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[29] GPIO[30] GPIO[31] Signal CCLKDS CCLKUS MSMBSMODE Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: Input ...
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... IDT 89HPES48T12 Data Sheet Signal P01MERGEN P23MERGEN P45MERGEN P67MERGEN P89MERGEN P1011MERGEN PERSTN RSTHALT SWMODE[3:0] Type Name/Description I Port 0 and 1 Merge. When this pin is asserted, port 1 is merged with port 0 to form a single x8 port. The SerDes lanes associated with port 1 become lanes 4 through 7 of port 0 ...
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... IDT 89HPES48T12 Data Sheet Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE APE Type Name/Description I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle ...
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... IDT 89HPES48T12 Data Sheet Pin Characteristics Note: Some input pads of the PES48T12 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...
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... IDT 89HPES48T12 Data Sheet Function PCI Express Interface (cont.) SMBus Interface General Purpose I/O System Pins Pin Name Type Buffer PE8RN[3:0] I CML PE8RP[3:0] I PE8TN[3:0] O PE8TP[3:0] O PE9RN[3:0] I PE9RP[3:0] I PE9TN[3:0] O PE9TP[3:0] O PE10RN[3:0] I PE10RP[3:0] I PE10TN[3:0] O PE10TP[3:0] O PE11RN[3:0] I PE11RP[3:0] I PE11TN[3:0] O PE11TP[3:0] O PEREFCLKN[3:0] I LVPECL/ CML PEREFCLKP[3:0] I REFCLKM ...
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... IDT 89HPES48T12 Data Sheet Function EJTAG / JTAG 1. Schmitt Trigger Input (STI) Pin Name Type Buffer JTAG_TCK I LVTTL JTAG_TDI I JTAG_TDO O JTAG_TMS I JTAG_TRST_N I Table 8 Pin Characteristics (Part I/O Internal Notes Type Resistor STI pull-up STI pull-up STI pull-up STI pull-up External pull-down ...
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... IDT 89HPES48T12 Data Sheet Logic Diagram — PES48T12 Reference Clock PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 1 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 3 PCI Express Switch SerDes Input Port 11 Master ...
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... IDT 89HPES48T12 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter PEREFCLK Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing ...
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... IDT 89HPES48T12 Data Sheet 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal GPIO 1 GPIO[31:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. ...
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... IDT 89HPES48T12 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express Analog Power PCI Express Serial Data Transmit ...
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... IDT 89HPES48T12 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below) ...
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... IDT 89HPES48T12 Data Sheet Note important for the reliability of this device in any user environment that the junction temperature not exceed the T specified in Table 16. Consequently, the effective junction to ambient thermal resistance ( maintained below the value determined by the formula: θ )/P JA ...
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... IDT 89HPES48T12 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V Differential peak-to-peak output voltage TX-DIFFp-p V De-emphasized differential output voltage TX-DE-RATIO V DC Common mode voltage ...
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... IDT 89HPES48T12 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. ...
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... IDT 89HPES48T12 Data Sheet Package Pinout — 1156-BGA Signal Pinout for PES48T12 The following table lists the pin numbers and signal names for the PES48T12 device. Pin Function Alt Pin GPIO_19 PE9TP03 ...
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... IDT 89HPES48T12 Data Sheet Pin Function Alt Pin GPIO_30 F2 E3 GPIO_31 GPIO_24 PE9RN03 F6 E7 PE9RN02 PE9RN01 F9 E10 PE9RN00 F10 E11 V F11 SS E12 PE8RN03 F12 E13 PE8RN02 F13 E14 V F14 SS E15 PE8RN01 ...
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... IDT 89HPES48T12 Data Sheet Pin Function Alt Pin GPIO_25 1 K9 J10 V K10 SS J11 V K11 SS J12 V K12 SS J13 V K13 SS J14 V PE K14 DD J15 V K15 SS J16 V K16 ...
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... IDT 89HPES48T12 Data Sheet Pin Function Alt Pin N1 PE11TP00 P1 N2 PE11TN00 PE11RP00 P4 N5 PE11RN00 N10 V PE P10 TT N11 V PE P11 DD N12 V PE P12 DD N13 V CORE P13 DD N14 V CORE P14 ...
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... IDT 89HPES48T12 Data Sheet Pin Function Alt Pin U1 PE11TP03 V1 U2 PE11TN03 PE11RP03 V4 U5 PE11RN03 PEREFCLKN2 U10 V PE V10 TT U11 V PE V11 DD U12 V PE V12 DD U13 V CORE V13 DD U14 V CORE V14 ...
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... IDT 89HPES48T12 Data Sheet Pin Function Alt Pin AA1 V AB1 SS AA2 V AB2 SS AA3 V AB3 SS AA4 V AB4 SS AA5 V AB5 SS AA6 V AB6 SS AA7 V AB7 SS AA8 V AB8 SS AA9 V PE AB9 DD AA10 V AB10 SS AA11 V PE AB11 DD AA12 V AB12 SS AA13 V CORE AB13 DD AA14 V CORE AB14 DD AA15 ...
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... IDT 89HPES48T12 Data Sheet Pin Function Alt Pin AE1 PE5TP00 AF1 AE2 PE5TN00 AF2 AE3 V AF3 SS AE4 PE5RP00 AF4 AE5 PE5RN00 AF5 AE6 V AF6 SS AE7 V AF7 SS AE8 V AF8 SS AE9 V IO AF9 DD AE10 V AF10 SS AE11 V AF11 SS AE12 V AF12 SS AE13 V PE AF13 TT AE14 ...
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... IDT 89HPES48T12 Data Sheet Pin Function Alt Pin AJ1 PE5TP03 AK1 AJ2 PE5TN03 AK2 AJ3 V AK3 SS AJ4 PE5RP03 AK4 AJ5 PE5RN03 AK5 AJ6 V AK6 SS AJ7 V AK7 SS AJ8 V AK8 SS AJ9 V AK9 SS AJ10 V AK10 SS AJ11 V AK11 SS AJ12 V AK12 SS AJ13 V AK13 SS AJ14 V AK14 SS AJ15 ...
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... IDT 89HPES48T12 Data Sheet Pin Function Alt Pin AN1 V AN18 SS AN2 V IO AN19 DD AN3 V AN20 SS AN4 SWMODE_0 AN21 AN5 SWMODE_2 AN22 AN6 V AN23 SS AN7 PE6TN00 AN24 AN8 PE6TN01 AN25 AN9 V AN26 SS AN10 PE6TN02 AN27 AN11 PE6TN03 AN28 AN12 V AN29 SS AN13 PE7TN00 ...
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... IDT 89HPES48T12 Data Sheet Power Pins V Core V Core DD DD N13 V19 N14 V21 N15 V22 N17 W13 N19 W14 N20 W16 N21 W18 N22 W20 P13 Y13 P15 Y15 P17 Y17 P19 Y19 P21 Y21 P22 Y22 R13 AA13 R14 AA14 ...
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... IDT 89HPES48T12 Data Sheet Ground Pins C16 A2 C17 A5 C18 A8 C19 A11 C20 A14 C21 A17 C22 A20 C23 A23 C24 A26 C25 A29 C26 A33 C27 A34 C28 B1 C29 B11 D11 B14 D14 B17 D17 B20 D20 ...
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... IDT 89HPES48T12 Data Sheet T10 V8 T11 V13 T12 V14 T13 V16 T14 V18 T16 V20 T18 V27 T20 V29 T23 V32 T24 W3 T25 W6 T26 W7 T27 W8 T28 W9 T29 W10 T32 W11 U3 W12 U6 W15 U8 W17 U15 W19 U17 W21 U19 ...
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... IDT 89HPES48T12 Data Sheet AL27 AM10 AL30 AM11 AM3 AM12 AM6 AM13 AM7 AM14 AM8 AM15 AM9 AM16 No Connect Pins NC NC V30 AA31 V31 AA33 V33 AA34 V34 AB30 W30 AB31 W31 AB33 W33 AB34 W34 AD30 AA30 AD31 ...
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... IDT 89HPES48T12 Data Sheet Signal Name GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 I/O Type Location I/O AM31 ...
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... IDT 89HPES48T12 Data Sheet Signal Name JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE NC P01MERGEN P23MERGEN P45MERGEN P67MERGEN P89MERGEN P1011MERGEN PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE1RN00 ...
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... IDT 89HPES48T12 Data Sheet Signal Name PE1RN01 PE1RN02 PE1RN03 PE1RP00 PE1RP01 PE1RP02 PE1RP03 PE1TN00 PE1TN01 PE1TN02 PE1TN03 PE1TP00 PE1TP01 PE1TP02 PE1TP03 PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE3RN00 PE3RN01 PE3RN02 PE3RN03 ...
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... IDT 89HPES48T12 Data Sheet Signal Name PE3RP01 PE3RP02 PE3RP03 PE3TN00 PE3TN01 PE3TN02 PE3TN03 PE3TP00 PE3TP01 PE3TP02 PE3TP03 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RP00 PE4RP01 PE4RP02 PE4RP03 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TP00 PE4TP01 PE4TP02 PE4TP03 PE5RN00 PE5RN01 PE5RN02 PE5RN03 PE5RP00 PE5RP01 PE5RP02 PE5RP03 ...
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... IDT 89HPES48T12 Data Sheet Signal Name PE5TN01 PE5TN02 PE5TN03 PE5TP00 PE5TP01 PE5TP02 PE5TP03 PE6RN00 PE6RN01 PE6RN02 PE6RN03 PE6RP00 PE6RP01 PE6RP02 PE6RP03 PE6TN00 PE6TN01 PE6TN02 PE6TN03 PE6TP00 PE6TP01 PE6TP02 PE6TP03 PE7RN00 PE7RN01 PE7RN02 PE7RN03 PE7RP00 PE7RP01 PE7RP02 PE7RP03 PE7TN00 PE7TN01 PE7TN02 PE7TN03 ...
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... IDT 89HPES48T12 Data Sheet Signal Name PE7TP01 PE7TP02 PE7TP03 PE8RN00 PE8RN01 PE8RN02 PE8RN03 PE8RP00 PE8RP01 PE8RP02 PE8RP03 PE8TN00 PE8TN01 PE8TN02 PE8TN03 PE8TP00 PE8TP01 PE8TP02 PE8TP03 PE9RN00 PE9RN01 PE9RN02 PE9RN03 PE9RP00 PE9RP01 PE9RP02 PE9RP03 PE9TN00 PE9TN01 PE9TN02 PE9TN03 PE9TP00 PE9TP01 PE9TP02 PE9TP03 ...
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... IDT 89HPES48T12 Data Sheet Signal Name PE10RN01 PE10RN02 PE10RN03 PE10RP00 PE10RP01 PE10RP02 PE10RP03 PE10TN00 PE10TN01 PE10TN02 PE10TN03 PE10TP00 PE10TP01 PE10TP02 PE10TP03 PE11RN00 PE11RN01 PE11RN02 PE11RN03 PE11RP00 PE11RP01 PE11RP02 PE11RP03 PE11TN00 PE11TN01 PE11TN02 PE11TN03 PE11TP00 PE11TP01 PE11TP02 PE11TP03 PEREFCLKN0 PEREFCLKN1 PEREFCLKN2 PEREFCLKN3 ...
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... IDT 89HPES48T12 Data Sheet Signal Name PEREFCLKP1 PEREFCLKP2 PEREFCLKP3 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE I/O Type Location I G17 AH18 I B32 I AH8 I AP3 I C34 I C33 I D33 ...
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... IDT 89HPES48T12 Data Sheet PES48T12 Pinout — Top View ...
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... IDT 89HPES48T12 Data Sheet PES48T12 Package Drawing — 1156-Pin BL1156/BR1156 April 16, 2008 ...
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... IDT 89HPES48T12 Data Sheet PES48T12 Package Drawing — Page Two April 16, 2008 ...
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... IDT 89HPES48T12 Data Sheet Revision History July 19, 2007: Initial publication of data sheet. November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements. April 16, 2008: In Table 16, Thermal Specifications, revised values for , , and . θ θ θ April 16, 2008 ...
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... IDT 89HPES48T12 Data Sheet Ordering Information A AAA NN Product Operating Device Family Voltage Family Valid Combinations 89HPES48T12ZABL 1156-ball FCBGA package, Commercial Temperature 89HPES48T12ZABR 1156-ball RoHS FCBGA package, Commercial Temperature 89HPES48T12ZABLI 1156-ball FCBGA package, Industrial Temperature 89HPES48T12ZABRI 1156-ball RoHS FCBGA package, Industrial Temperature ...