89hpes48t12 Integrated Device Technology, 89hpes48t12 Datasheet - Page 11
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89hpes48t12
Manufacturer Part Number
89hpes48t12
Description
48-lane, 12-port Pcie I/o Connectivity Switch
Manufacturer
Integrated Device Technology
Datasheet
1.89HPES48T12.pdf
(47 pages)
- Current page: 11 of 47
- Download datasheet (2Mb)
Pin Characteristics
IDT 89HPES48T12 Data Sheet
Note: Some input pads of the PES48T12 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
PCI Express Interface
Function
Pin Name
PE0RN[3:0]
PE0RP[3:0]
PE1RN[3:0]
PE1RP[3:0]
PE2RN[3:0]
PE2RP[3:0]
PE3RN[3:0]
PE3RP[3:0]
PE4RN[3:0]
PE4RP[3:0]
PE5RN[3:0]
PE5RP[3:0]
PE6RN[3:0]
PE6RP[3:0]
PE7RN[3:0]
PE7RP[3:0]
PE0TN[3:0]
PE0TP[3:0]
PE1TN[3:0]
PE1TP[3:0]
PE2TN[3:0]
PE2TP[3:0]
PE3TN[3:0]
PE3TP[3:0]
PE4TN[3:0]
PE4TP[3:0]
PE5TN[3:0]
PE5TP[3:0]
PE6TN[3:0]
PE6TP[3:0]
PE7TN[3:0]
PE7TP[3:0]
Table 8 Pin Characteristics (Part 1 of 3)
Type
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
11 of 47
Buffer
CML
Serial Link
Type
I/O
Resistor
Internal
Notes
April 16, 2008
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