mh2040 Music Semiconductors, Inc., mh2040 Datasheet - Page 13

• Manufacturer Part Number: mh2040
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

REGISTER DESCRIPTIONS
The Comparand register, seven mask registers, Address
register, Configuration register, Status register, Next Free
Address register, Device Select register, and Instruction
register comprise the register set. Note that all
RESERVED bits can be read and written without affecting
the operation of the device.
However, for forward compatibility with future product
enhancements, system designers should not rely on any
particular RESERVED bit having no effect on the
operation of the device in future revisions. Therefore all
RESERVED bits should be set to logical zero.
The Register Set
Comparand Register
The 64-bit Comparand register holds the value to be
compared with the valid contents of the Address Database
array, although the DQ lines can be compared directly, and
then optionally written into the Comparand register.
Mask Registers
There are seven 64-bit mask registers that are used to mask
Compare and Write cycles. When a bit is set LOW in a
selected mask register, the corresponding bit enters into
comparison during a Compare cycle, or is written during a
Write cycle. When a bit is set HIGH in a selected mask
register, the corresponding bit does not enter into
comparison during a Compare cycle, or remains
unchanged after a Write cycle.
Address Register
The 32-bit Address register is used for indirect addressing
of the Address Database. When random access to the
Address Database is restricted to indirect addressing, the
width of the control bus can be reduced to 9 bits if
masking is used or 6 bits if it is not. Control states allow
increment and decrement of the Address register as well as
auto-increment and auto-decrement Read and Write
cycles. Bits AR11-0 hold the address while bits AR31-12
are reserved and should be set LOW.
Configuration Register
The 32-bit Configuration register sets the persistent
operating conditions of the MH2040. Bits FR31-29 select
which mask register is used for direct Write cycles to the
Address database when the address is conveyed on the AC
bus (/AV=LOW), a value of 000 in this field results in
unmasked direct Write cycles. Bits FR27-26 select the
mode of operation: Hardware Control mode or Software
Control mode. Bit FR25 is used to identify the
lowest-priority device in a vertically cascaded system. Bits
FR3-0 hold the device Page address. All other bits are
reserved and should be set LOW. See Table 3.
Rev. 1.0
HARRP - HLA Packaged Asynchronous Data Recognition-Recall Processors
13
Status Register
The 32-bit Status register holds the results of the most
recent control state that caused the PA:AA lines to change.
It is intended for use in Software Control mode where
results of an operation are read from the MU9C through
the DQ31-0 lines. Bit SR30 holds the Match flag, /MF,
which goes LOW when there is a match in the Address
Database. Bit SR29 holds an internal version of the
Multiple Match flag, /MM, which is LOW if there is a
multiple match in the particular device; note that this is not
a system-level multiple match indication. Bit SR28 holds
the Full flag, /FF, which goes LOW when all the Address
Database locations are set valid, and the /FI line is LOW.
Bits SR25-24 indicate the type of result held in the Active
Address field: Match address, Memory Access address, or
Reset state. Bits SR19-16 hold the Page address, PA3-0,
for the device. Bits SR11-0 hold the Active address,
identical to that on the AA bus. All other bits are reserved
and are set LOW. See Table 4.
Next Free Address Register
The 32-bit Next Free Address register holds the
highest-priority address that has its Validity bit set empty
(HIGH). System-level prioritization ensures that only the
device with the highest-priority empty address in a
vertically cascaded system will respond to a Read Next
Free Address Register Control state. Bits NF19-16 hold
the device Page address, PA3-0. Bits NF11-0 hold the next
free address value. All other bits are reserved, and are set
LOW. See Table 5.
Device Select Register
The 32-bit Device Select register is used for software
selection of the MH2040 . A particular device is selected
when the value in bits DS3-0 are the same as the Page
Address value PA3-0 and the Device Select Enable bit,
DS8, is set LOW. Setting DS8 HIGH prevents the Device
Select register from enabling the MH2040 . All other bits
are reserved and should be set LOW. See Table 6.
Instruction Register
In Software Control mode, control states are written to the
32-bit Instruction register instead of being fed to the
MH2040 through the DSC and AC8-0 lines. Bits IR12-0
are equivalent to the DSC and AC8-0 lines and the control
states they invoke are identical to those of the Hardware
Control mode (direct addressing is not supported in
Software mode, AC11-9 are not used). The remaining bits
are reserved and should be set LOW.