mh2040 Music Semiconductors, Inc., mh2040 Datasheet - Page 22

• Manufacturer Part Number: mh2040
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS
Description: Writes data from the DQ31-0 bus to bits
31-0 (DSC LOW) or 63-32 (DSC HIGH) of the location
defined by the contents of the Address register. The
validity of the location is set by the state of the /VB input,
/VB = LOW: Valid, /VB = HIGH: Empty. The write is
masked by bits 31-0 (DSC LOW) or 63-32 (DSC HIGH)
of the contents of Mask Register nnn. When nnn=000 no
mask is used; when masking is selected, only bits in the
addressed location that correspond to LOW values in the
selected mask register are updated. The contents of the
Address register are incremented.
Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH /AV: HIGH PA:AA: aaa Scope: S
Description: Reads data from bits 31-0 (DSC LOW) or
63-32 (DSC HIGH) of the location defined by the contents
of the Address register to the DQ31-0 bus. This control
state provides indirect random access memory reads.
During the Read cycle, the /VB line carries the Validity Bit
value of the addressed location. The contents of the
Address register are incremented.
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS
Description: Writes data from bits 31-0 (DSC LOW) or
63-32 (DSC HIGH) of the DQ31-0 bus to the location
defined by the contents of the Address register. The
validity of the location is set by the state of the /VB input,
/VB = LOW: Valid, /VB = HIGH: Empty. The write is
masked by bits 31-0 (DSC LOW) or 63-32 (DSC HIGH)
of the contents of Mask Register nnn. When nnn=000 no
mask is used; when masking is selected, only bits in the
addressed location that correspond to LOW values in the
selected mask register are updated. The contents of the
Address register are decremented.
HARRP - HLA Packaged Asynchronous Data Recognition-Recall Processors
Indirect Write at Address;
Increment Address Register
WRs[AR]+{MRnnn}
XXX nnn 100 110
Indirect Read at Address;
Increment Address Register
RDs[AR]+
XXX XXX 100 110
Indirect Write at Address;
Decrement Address Register
WRs[AR]-{MRnnn}
XXX nnn 100 111
22
Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH /AV: HIGH PA:AA: aaa Scope: S
Description: Reads data from bits 31-0 (DSC LOW) or
63-32 (DSC HIGH) of the location defined by the contents
of the Address register to the DQ31-0 bus. This control
state provides indirect random access memory reads.
During the Read cycle, the /VB line carries the Validity Bit
value of the addressed location. The contents of the
Address register are decremented.
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: HPMA Scope: HPD
Description: Writes data from the DQ31-0 bus to bits
31-0 (DSC LOW) or 63-32 (DSC HIGH) of the
highest-priority matching location in the Memory array.
The validity of the location is set by the state of the /VB
input, /VB=LOW: Valid, /VB=HIGH: Empty. The write is
masked by bits 31-0 (DSC LOW) or 63-32 (DSC HIGH)
of the contents of Mask Register nnn. When nnn=000 no
mask is used; when masking is selected, only bits in the
addressed location that correspond to LOW values in the
selected mask register are updated.
Control State:
Mnemonic:
Binary Op-Code: XXX XXX 000 010
/W: HIGH /AV: HIGH PA:AA: HPMA Scope: HPD
Description: Reads data from bits 31-0 (DSC LOW) or
63-32 (DSC HIGH) the location defined by the
highest-priority matching location to the DQ31-0 bus. In
the event that the previous Comparison cycle resulted in a
mismatch, the DQ31-0 bus will remain in high-impedance.
RDs[AR]-
Read Highest-Priority
Indirect Read at Address;
Decrement Address Register
XXX XXX 100 111
Write to Highest-Priority
Matching Location
WRs[HPM]{MRnnn}
XXX nnn 000 010
Matching Location
RDs[HPM]
Rev. 1.0