zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 34

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

1.7.6 UART0/1
Serial communication is categorized as synchronous mode or asynchronous mode in terms of
its data transmission method.
The embedded MCU has both UART0 and UART1 to enable two-way communication.
These devices support asynchronous mode. The following registers are used to control UART.
RBR (UART0 RECEIVE BUFFER REGISTER, 0x2500)
THR (UART0 TRANSMITTER HOLDING REGISTER, 0x2500)
DLL (UART0 DIVISOR LSB REGISTER, 0x2500)
Note: After the data is written to the DLM register, it should be written in this register. When the data is
written to DLL register, the clock divisor begins. Baud rate is calculated by the following equation.
IER (UART0 INTERRUPT ENABLE REGISTER, 0x2501)
DLM (UART0 DIVISOR LATCH MSB REGISTER, 0x2501)
IIR (UART0 INTERRUPT IDENTIFICATION REGISTER, 0x2502)
Note: IIR register uses the same address as FCR register in Table 19 below. IIR register is read-only
and FCR register is write-only.
Bit
7:0
7:0
7:0
7:4
7:0
7:4
3:1
3
2
1
0
0
Rev A
Baud rate = clock_speed / (7 × divisor_latch_value)
PENDING
ERBEI
EDSSI
ETBEI
Name
INTID
RBR
ELSI
DLM
THR
DLL
Read the received data
This register stores the data to be transmitted. The address is the
same as the RBR register. When accessing this address, received
data (RBR) is read and the data to be transmitted is stored.
This register can be accessed only when the DLAB bit in the LCR
register is set to ‘1’. This register shares a 16-bit register with the
DLM register (below) occupying the lower 8 bits. This full 16-bit
register is used to divide the clock.
Reserved
Enable MODEM Status Interrupt.
When this field is set to ‘1’, Modem status interrupt is enabled.
Enable Receiver Line Status Interrupt.
Enable Transmitter Holding Register Empty Interrupt
Enable Received Data Available Interrupt
This register can be accessed only when the DLAB bit in the LCR
register is set to ‘1’. This register shares a 16-bit register with the
DLL register (above) occupying the higher 8 bits. This full 16-bit
register is used to divide the clock.
Reserved
Interrupt Identification. Refer to the Table
Shows whether the interrupt is pending or not. When this field is
‘0’, the interrupt is pending.
Document No. 0005-05-07-00-000
Table 17 – UART0 Registers
ZIC2410 Datasheet
Descriptions
18
.
R/W
W/O
R/W
R/W
R/W
R/W
R/W
R/W
R/O
R/O
R/O
R/O
Page 34 of 119
Reset
Value
0x00
0x00
0x00
0x00
0
0
0
0
0
0
0
1