zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 39

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

1.7.7 SPI MASTER/SLAVE
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). The operation is different in either Master mode or Slave mode
In the Master mode, the data transmission is done by writing to the SPDR (SPI Data Register,
0x2542). After transmission, data reception is initiated by a byte transmitted to the Slave device
from the Master SPI clock. When the SPI interrupt occurs, the value of the SPDR register
becomes the received data from the SPI slave device. Even though the SPDR TX and RX have
the same address, no data collision occurs because the processes of writing and reading data
happen sequentially.
In the Slave mode, the data must be ready in the SPDR when the Master calls for it. Data
transmission is accomplished by writing to the SPDR before the SPI clock is generated by the
Master. When the Master generates the SPI clock, the data in the SPDR of the Slave is
transferred to the Master. If the SPDR in the Slave is empty, no data exchange occurs. Data
reception is done by reading the SPDR when the next SPI interrupt occurs.
SPCR (SPI CONTROL REGISTER, 0x2540)
Bit
1:0
7
6
5
4
3
2
Rev A
MSTR
CPHA
Name
CPOL
SPIE
SPR
SPE
SPI Interrupt Enable. When this field is set to ‘1’, SPI interrupt is
enabled.
SPI Enable. When this field is set to ‘1’, SPI is enabled.
Reserved
Master Mode Select. When this field is set to ‘1’, a Master mode is
selected.
Clock Polarity. If there is no data transmission while this field is
set to ‘0’, SCK pin retains ‘0’. If there is no data transmission while
this field is set to ‘1’, SCK pin retains ‘1’. This field is used to set
the clock and data between a Master and Slave with CPHA field.
Refer to information below for a more detailed explanation.
Clock Phase. Used to set the clock and data between a Master
and Slave with CPOL field. See details below.
SPI Clock Rate Select. With ESPR field in SPER register
(0x2543), selects SPI clock (SCK) rate when the device is
configured as a Master. Refer to the ESPR field in Table 25.
Table 23 – SPI Control Registers
Figure 17 – SPI Data Transfer
Document No. 0005-05-07-00-000
ZIC2410 Datasheet
Descriptions
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Page 39 of 119
Reset
Value
0
0
0
1
0
0
0