co561ad-l Connect One Ltd., co561ad-l Datasheet - Page 16

• Manufacturer Part Number: co561ad-l
• Description: The Co561ad-l Ichip Lan? Internet Controller? Is Part Of A Family Of Intelligent Peripheral Devices That Provides Internet Connectivity Solutions To A Myriad Of Embedded Devices.
• Manufacturer: Connect One Ltd.

11-3700-00
5.2 iChip LAN Pin Functional Descriptions
5.2.1 Local BUS Signals
A[19:0]
AD[15:0]
ALE
-UCS
-LCS
iChip CO561AD-L Datasheet
Signal
Type
O/I
O
O
O
O
45, 49, 47,
51, 48, 53,
56, 54, 38,
37, 33, 46,
36, 35, 34,
25, 10, 11,
23, 13, 16,
50, 39, 8,
17, 22, 9,
24, 2, 3,
Pin No.
4, 5, 6,
19, 57
41
14
21
7
Address BUS: These pins supply addresses to the
system one-half of a CLKO period earlier than the
multiplexed address and data BUS AD15–AD0.
During a BUS hold or reset condition, the address
BUS is in a HIGH-impedance state.
These pins should be Connected to the address bus
of the LAN controller.
Address and Data BUS: These time-multiplexed
pins supply addresses and data to the system. This
BUS will supply an address to the system during the
first period of a BUS cycle. They supply data to the
system during the remaining periods of that cycle.
During a BUS hold or reset condition, the address
BUS is in a HIGH-impedance state.
These pins should be connected to the data bus of
the LAN controller.
Address Latch Enable: This pin indicates to the
system that an address appears on the address and
data BUS (AD15–AD0). The address is guaranteed
to be valid on the trailing edge of ALE.
This pin should be left Not Connected.
Upper Chip Select: When –UCS is LOW, the iChip
LAN accesses internal flash memory.
This pin should be left Not Connected.
Lower Chip Select: When –LCS is LOW, the iChip
LAN accesses internal SRAM memory.
This pin should be left Not Connected.
Description
Pin Descriptions
5-2