scn68681 NXP Semiconductors, scn68681 Datasheet - Page 12

• Manufacturer Part Number: scn68681
• Description: Dual Asynchronous Receiver/transmitter Duart
• Manufacturer: NXP Semiconductors

applied via CRA. After reading or writing MR1A, the pointer will point
Philips Semiconductors
Table 2.
MR1A – Channel A Mode Register 1
MR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
to MR2A.
MR1A[7] – Channel A Receiver Request-to-Send Control
This bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR1A[7] = 1 causes RTSAN to be
negated upon receipt of a valid start bit if the Channel A FIFO is full.
However, OPR[0] is not reset and RTSAN will be asserted again
when an empty FIFO position is available. This feature can be used
for flow control to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input of the transmitting
device.
MR1A[6] – Channel A Receiver Interrupt Select
This bit selects either the Channel A receiver ready status (RxRDY)
or the Channel A FIFO full status (FFULL) to be used for CPU
interrupts. It also causes the selected bit to be output on OP4 if it is
programmed as an interrupt output via the OPCR.
2004 Mar 02
Dual asynchronous receiver/transmitter (DUART)
CTUR
CTLR
IPCR
ACR
IMR
ISR
IVR
Register Bit Formats
BRG SET
CHANGE
IN. PORT
CHANGE
SELECT
0 = set 1
1 = set 2
0 = No
1 = Yes
0 = No
1 = Yes
0 = Off
1 = On
C/T[15]
DELTA
INPUT
IVR[7]
PORT
C/T[7]
BIT 7
BIT 7
BIT 7
BIT 7
BIT 7
BIT 7
BIT 7
INT
IP3
BREAK B
BREAK B
0 = No
1 = Yes
0 = No
1 = Yes
0 = Off
1 = On
C/T[14]
DELTA
DELTA
DELTA
IVR[6]
C/T[6]
BIT 6
BIT 6
BIT 6
BIT 6
BIT 6
BIT 6
BIT 6
INT
IP2
(Continued)
MODE AND SOURCE
COUNTER/TIMER
See Table 4
FFULLB
FFULLB
0 = No
1 = Yes
RxRDY/
0 = No
1 = Yes
RxRDY/
0 = Off
1 = On
C/T[13]
DELTA
C/T[5]
IVR[5]
BIT 5
BIT 5
BIT 5
BIT 5
BIT 5
BIT 5
BIT 5
INT
IP1
TxRDYB
TxRDYB
0 = No
1 = Yes
0 = No
1 = Yes
0 = Off
1 = On
C/T[12]
DELTA
BIT 4
C/T[4]
IVR[4]
BIT 4
BIT 4
BIT 4
BIT 4
BIT 4
BIT 4
12
IP0
INT
is programmed by MR1A[4:3], and the polarity of the forced parity bit
parity’ mode is programmed. In the special multidrop mode it selects
MR1A[5] – Channel A Error Mode Select
This bit select the operating mode of the three FIFOed status bits
(FE, PE, received break) for Channel A. In the ‘character’ mode,
status is provided on a character-by-character basis; the status
applies only to the character at the top of the FIFO. In the ‘block’
mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command for Channel
A was issued.
MR1A[4:3| – Channel A Parity Mode Select
If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] = 11 selects Channel A to operate in the
special multidrop mode described in the Operation section.
MR1A[2] – Channel A Parity Type Select
This bit selects the parity type (odd or even) if the ‘with parity’ mode
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
the polarity of the A/D bit.
COUNTER
COUNTER
0 = Off
1 = On
IP3 INT
DELTA
0 = LOW
1 = HIGH
0 = No
1 = Yes
0 = Off
1 = On
READY
READY
C/T[11]
BIT 3
IVR[3]
C/T[3]
BIT 3
BIT 3
BIT 3
BIT 3
BIT 3
BIT 3
INT
IP3
BREAK A
BREAK A
0 = Off
1 = On
IP2 INT
DELTA
0 = LOW
1 = HIGH
0 = No
1 = Yes
0 = Off
1 = On
C/T[10]
DELTA
DELTA
BIT 2
IVR[2]
C/T[2]
BIT 2
BIT 2
BIT 2
BIT 2
BIT 2
BIT 2
INT
IP2
0 = Off
1 = On
IP1 INT
FFULLA
FFULLA
DELTA
0 = LOW
1 = HIGH
RxRDY/
0 = No
1 = Yes
RxRDY/
0 = Off
1 = On
BIT 1
C/T[9]
C/T[1]
IVR[1]
BIT 1
BIT 1
BIT 1
BIT 1
BIT 1
BIT 1
INT
IP1
SCN68681
Product data
0 = Off
1 = On
TxRDYA
TxRDYA
IP0 INT
DELTA
0 = LOW
1 = HIGH
0 = No
1 = Yes
0 = Off
1 = On
BIT 0
C/T[8]
C/T[0]
IVR[0]
BIT 0
BIT 0
BIT 0
BIT 0
BIT 0
BIT 0
IP0
INT