scn2681t NXP Semiconductors, scn2681t Datasheet - Page 4

• Manufacturer Part Number: scn2681t
• Description: Dual Asynchronous Receiver/transmitter Duart
• Manufacturer: NXP Semiconductors

Refer to SCN2681 for functional description.
Philips Semiconductors
PIN CONFIGURATION
NOTE:
PIN DESCRIPTION
2004 Mar 22
MNEMONIC
Dual asynchronous receiver/transmitter (DUART)
RESET
X1/CLK
D0–D7
A0–A3
INTRN
WRN
RDN
CEN
X2
TYPE
I/O
O
I
I
I
I
I
I
I
Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the DUART and
the CPU. D0 is the least significant bit.
Chip Enable: Active LOW input signal. When LOW, data transfers between the CPU and the DUART are enabled on
D0–D7 as controlled by the WRN, RDN, and A0–A3 inputs. When CEN is HIGH, the DUART places the D0–D7 lines
in the three-state condition.
Write Strobe: When LOW and CEN is also LOW, the contents of the data bus is loaded into the addressed register.
The transfer occurs on the rising edge of the signal.
Read Strobe: When LOW and CEN is also LOW, causes the contents of the addressed register to be presented on
the data bus. The read cycle begins on the falling edge of RDN.
Address Inputs: Select the DUART internal registers and ports for read/write operations.
Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the HIGH state,
stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark
(HIGH) state. Clears Test modes, sets MR pointer to MR1.
Interrupt Request: Active-LOW, open-drain output which signals the CPU that one or more of the eight maskable
interrupting conditions are true.
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally
3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.
Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not connected although it
is permissible to ground it.
CORNER
INDEX
PIN/FUNCTION
17
7
10 RDN
11 RxDB
12 NC
13 TxDB
14 OP1
15 OP3
16 OP5
17 OP7
18 D1
19 D3
20 D5
21 D7
22 GND
1
2
3
4
5
6
7
8
9
Figure 2. Pin configuration
18
6
NC
A0
IP3
A1
IP1
A2
A3
IP0
WRN
TOP VIEW
PLCC
1
PIN/FUNCTION
4
NAME AND FUNCTION
SD00738
23 NC
24 INTRN
25 D6
26 D4
27 D2
28 D0
29 OP6
30 OP4
31 OP2
32 OP0
33 TxDA
34 NC
35 RxDA
36 X1/CLK
37 X2
38 RESET
39 CEN
40 IP2
41 IP6
42 IP5
43 IP4
44 V
40
28
CC
39
29
SCN2681T
Product data