hi-3585 Holt Integrated Circuits, Inc., hi-3585 Datasheet - Page 7

• Manufacturer Part Number: hi-3585
• Description: Terminal Ic With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
Once a valid ARINC word is loaded into the FIFO, the EOS signal
clocks the Data Ready flip-flop to a "1" and Status Register bit 0
(SR0) to a “0”. The SR0 bit remains low until the Receive FIFO is
empty.
interface using SPI instruction 08 hex to read a single word, or
09 hex to empty the entire Receive FIFO.
Up to 32 ARINC words may be held in the Receive FIFO. Status
register bit 2 (SR2) goes high when the Receive FIFO is full.
Failure to unload the Receive FIFO when full causes additional
received valid ARINC words to overwrite Receive FIFO location 32.
16 or more ARINC words. SR1 may be interrogated by the system’s
external microprocessor, allowing a 16 word data retrieval routine
to be performed.
LABEL RECOGNITION
The user loads the 256-bit label look-up table to specify which 8-bit
incoming ARINC labels are captured by the receiver, and which are
discarded. Setting a “1” in the look-up table enables processing of
received ARINC words containing the corresponding label. A “0” in
the look-up table causes discard of received ARINC words
containing the label. The 256-bit look-up table is loaded using SPI
op codes 02 hex, 03 hex or 06 hex, as described in Table 1. After
the look-up table is initialized, set Control Register bit CR2 to
enable label recognition.
If label recognition is enabled, the receiver compares the label in
each new ARINC word against the stored look-up table. If a label
match is found, the received word is processed. If no match
occurs, the new ARINC word is discarded and no indicators of
received ARINC data are presented.
A FIFO half-full flag (SR1) is high when the Receive FIFO contains
SCK
SO
CS
SI
Each received ARINC word is retrieved via the SPI
LOAD SHIFT REGISTER
32 BIT PARALLEL
32 x 32 FIFO
SPI INTERFACE
SPI COMMANDS
SPI COMMANDS
FIGURE 3.
ADDRESS
LOAD
HOLT INTEGRATED CIRCUITS
BIT CLOCK
WORD CLOCK
TRANSMITTER BLOCK DIAGRAM
GENERATOR
HI-3585
CR3, CR9
PARITY
CR10, CR1
7
READING THE LABEL LOOK-UP TABLE
The contents of the Label Look-up table may be read via the SPI
interface using instruction 0D hex as described in Table 1.
TRANSMITTER
FIFO OPERATION
The Transmit FIFO is loaded with ARINC 429 words awaiting
transmission. SPI op code 0E hex writes up to 32 ARINC words
into the FIFO, starting at the next available FIFO location. If Status
Register bit SR3 equals “1” (FIFO empty), then up to 32 words (32
bits each) may be loaded. If Status Register bit SR3 equals “0”
then only the available positions may be loaded. If all 32 positions
are full, Status Register bit SR5 is asserted. Further attempts to
load the Transmit FIFO are ignored until at least one ARINC word is
transmitted.
The Transmit FIFO half-full flag (Status Register bit SR4) equals “0”
when the Transmit FIFO contains less than 16 words. When SR4
equals “0”, the system microprocessor can safely initiate a 16-word
ARINC block-write sequence.
In normal operation (Control Register bit CR3 = ”1”), the 32nd bit
transmitted is a word parity bit. Odd or even parity is selected by
programming Control Register bit CR9 to a “0” or “1” respectively. If
Control Register bit CR3 equals “0”, all 32 bits loaded into the
Transmit FIFO are treated as data and are transmitted.
SPI op code 11 hex asynchronously clears all data in the Transmit
FIFO. The Transmit FIFO should be cleared after a self-test before
starting normal operation to avoid inadvertent transmission of test
data.
CLOCK
DATA
SEQUENCER
NULL TIMER
DATA AND
WORD COUNTER
FIFO CONTROL
DATA CLOCK
SEQUENCER
WORD GAP
COUNTER
LOADING
DIVIDER
AND
FIFO
AND
BIT
SEQUENCE
WORD COUNT
INCREMENT
START
LINE DRIVER
AOUT
BOUT
CR12
ACLK
SR3
SR4
SR5