hi-3588pqt Holt Integrated Circuits, Inc., hi-3588pqt Datasheet
hi-3588pqt
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hi-3588pqt Summary of contents
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... RINB - directly N N Pin Plastic Quad Flat Pack (PQFP) HOLT INTEGRATED CIRCUITS www.holtic.com HI-3588 ARINC 429 (Top View GND HI-3588PCI N/C HI-3588PCT RFLAG - GND 29 - N/C HI-3588PQI 28 - N/C HI-3588PQT RFLAG N/C 05/08 ...
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... SPI interface serial data input CS INPUT Chip select. Data is shifted into SI and out of SO when SCK INPUT SPI Clock. Data is shifted into or out of the SPI interface using SCK GND POWER Chip 0V supply. Note BOTH GND pins MUST be connected ACLK INPUT Master timing source for the ARINC 429 receiver ...
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... INSTRUCTIONS Instruction op codes are used to read, write and configure the HI- 3588A. When CS goes low, the next 8 clocks at the SCK pin shift an instruction op code into the decoder, starting with the first positive edge. The op code is fed into the SI pin, most significant bit first ...
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... Not used ARINC 429 DATA FORMAT Not used Control Register bit CR11 controls how individual bits in the received ARINC word are mapped to the HI-3588 SPI data word bits during data read or write operations. The following table describes this mapping: Not used ...
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... A word gap Null requires at least three consecutive Null sam- ples (three high bits) in the upper half of the Null sampling shift register and at least three consecutive Null samples (three high bits) in the lower half of the Null sampling shift reg- COMPARATORS ister. This guarantees the minimum pulse width. ...
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... When using the RINA/B-40 pins, each side of the ARINC bus must be connected through a 40K ohm series resistor in order for the chip to detect the correct ARINC levels. The typical 10 Volt dif- ferential signal is translated and input to a window comparator and latch. The comparator levels are set so that with the external 40K ohm resistors, they are just below the standard 6 ...
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... FIFO status RFLAG pin is also cleared. The Control Register is not affected by Master Reset. TIMING DIAGRAMS CS t CHH SCK SCKH SCKL SCK SO Hi Impedance TXAOUT ARINC BIT TXBOUT DATA NULL BIT 30 BIT 31 ARINC DATA BIT 32 RFLAG t RFLG CS SPI INSTRUCTION 08h, (or 09h ...
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... PD CS Pin Output Sink OUT Output Source OUT C O VDD I DD HOLT INTEGRATED CIRCUITS 8 (Hi-Temp): .....-55°C to +125°C LIMITS MIN TYP 6.5 10.0 -13.0 -10.0 -2 140 - 140 - 100 -450 80% VDD 20% VDD -1.5 250 -600 = -100 A µ 90%VDD = 1.0mA 10% VDD = 0.4V 1 ...
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... SPI SI Data hold time after SCK rising edge SO high-impedance after SCK falling edge RECEIVER TIMING Delay - Last bit of received ARINC word to RFLAG(Full or Empty Speed Delay - Last bit of received ARINC word to RFLAG(Full or Empty Speed Received data available to SPI interface. RFLAG to SPI receiver read or clear FIFO instruction to RFLAG ...
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... REVISION HISTORY Revision Date Page Description of Change DS3588, Rev. NEW 05/08/08 All HI-3588 Initial Release HOLT INTEGRATED CIRCUITS 10 ...
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... PLASTIC CHIP-SCALE PACKAGE (QFN) .276 BSC (7.00) .276 Top View BSC (7.00) .039 max (1.00) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) .547 ± .010 (13.90 ± .25) SQ. See Detail A ...