hi-3596 Holt Integrated Circuits, Inc., hi-3596 Datasheet - Page 8

• Manufacturer Part Number: hi-3596
• Description: Octal Arinc 429 Receivers With Label Recognition And Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

3. To validate the receive data bit rate, each bit must
4. Following the last data bit of a valid reception, the
Receiver Parity
If enabled by setting Control Register CR4 bit to “1”, the
receiver parity circuit counts Ones received, including
the parity bit. If the result is odd, then a “0” appears in
the 32
Setting Control Register CR4 bit to “0” disables parity
checking and all 32 bits are treated as data.
Retrieving Data
Once 32 valid bits are recognized, the receiver logic
generates an End of Sequence (EOS). Depending on
the state of Control Register bits CR2, CR6, CR7 and
CR8, the received 32-bit ARINC word is then checked
for correct decoding and label match before it is loaded
into the 4 x 32 Receive FIFO. ARINC words that do not
match required 9th and 10th ARINC bit and do not have
a label match are ignored and are not loaded into the
Receive FIFO. Table 9 describes this operation.
Table 8. Acceptable Data Bit Rates at 1MHz Input
follow its preceding bit by not less than 8 samples
and not more than 12 samples. With exactly 1MHz
input clock frequency, the acceptable data bit rates
are shown in Table 8.
Word Gap timer samples the Null shift register every
10 input clocks (every 80 clocks for low speed). If
a Null is present, the Word Gap counter is incre-
mented. A Word Gap count of 3 enables the next
reception.
Data Bit Rate Max
Data Bit Rate Min
nd
bit.
Clock Frequency
HIGH SPEED
125Kbps
83Kbps
HI-3596, HI-3597, HI-3598, HI-3599
LOW SPEED
HOLT INTEGRATED CIRCUITS
10.4Kbps
15.6Kbps
8
Once a valid ARINC word is loaded into the FIFO, the
EOS signal clocks the Data Ready fl ip-fl op to a “1”,
and the corresponding channel’s Status Register FIFO
Empty bit (SR0- SR7) goes to a “0”. The channel’s
Empty bit remains low until the corresponding Receive
FIFO is empty. Each received ARINC word is retrieved
via the SPI interface using SPI instruction n3 hex where
“n” is the channel number 1-8 hex.
Up to 4 ARINC words may be held in each channel’s
Receive FIFO. The Status Register FIFO Full bit (SR8
- SR15) goes high when the corresponding channel’s
Receive FIFO is full. Failure to offl oad a full Receive
FIFO causes additional received valid ARINC words to
overwrite the last received word.
Label Recognition
The user loads the 16 byte label look-up table to spec-
ify which 8-bit incoming ARINC labels are captured by
the receiver, and which are discarded. If fewer than 16
labels are required, spare label memory locations must
be fi lled with duplicate copies of any valid label. After the
look-up table is initialized, set channel Control Register
bit CR2 to enable label recognition for that channel.
If label recognition is enabled, the receiver compares
the label in each new ARINC word against the channel’s
stored label look-up table. If a label match is found, the
received word is processed. If no match occurs, the new
ARINC word is discarded and no indicators of received
ARINC data are presented. Note that 00 hex is treated
in the same way as any other label value. Label memory
bit signifi cance is not changed by the status of Control
Register bit CR9. The most signifi cant label bit is always
CR2
0
1
1
0
0
1
1
1
1
ARINC word
matches
Enabled
label
Yes
Yes
Yes
Table 9. FIFO Loading Control
No
No
No
X
X
X
CR6
0
0
0
1
1
1
1
1
1
match CR7, 8
ARINC word
bits 10, 9
Yes
Yes
Yes
No
No
No
X
X
X
Ignore Data
Ignore Data
Ignore Data
Ignore Data
Ignore Data
Load FIFO
Load FIFO
Load FIFO
Load FIFO
FIFO