hi-3210 Holt Integrated Circuits, Inc., hi-3210 Datasheet - Page 31

• Manufacturer Part Number: hi-3210
• Description: Arinc 429 Data Management Engine / Octal Receiver / Quad Transmitter
• Manufacturer: Holt Integrated Circuits, Inc.

3
2
1
0
LOWER BIST FAIL ADDRESS REGISTER
(Address 0x8071)
UPPER BIST FAIL ADDRESS REGISTER
(Address 0x8072)
---------
RBFAIL
RBPASS
RBSTRT
Writing logic 1 to this bit initiates the RAM BIST test selected by register bits RBSEL2:0. The RBSTRT
Not Used.
RAM BIST Fail.
Device logic asserts this bit when failure occurs while performing the selected RAM test. This bit is
RAM BIST Pass.
Device logic asserts this bit when the selected RAM test completes without error. This bit is
5. Write an incrementing pattern into sequential RAM locations from 0x0000 to 0x7FFF
6. Read each memory location from 0x0000 to 0x7FFF and verify the contents
7. Write 1s complement of each cell’s current contents, into each RAM location (same addr range)
8. Read each memory location and verify the contents
RAM BIST Start.
bit can only be set in MODE2:0 = 0x04. This bit is automatically cleared upon test completion.
Register bits 1:0 indicate fail / pass test result.
automatically cleared when RBSTRT bit 3 is set. When BIST failure occurs, a clue to the failing RAM
address can be read at register addresses 0x8071 and 0x8072. For speed, the RAM BIST
concurrently tests four consecutive RAM addresses in parallel. If a test failure occurs, register
addresses 0x8071 and 0x8072 can be used to determine the four RAM addresses tested.
automatically cleared when RBSTRT bit 3 is set.
HOLT INTEGRATED CIRCUITS
f.
g. Write then read and verify 0xF0
h. Write then read and verify 0x00
I.
j.
Write then read and verify 0x0F
Write then read and verify 0xFF
Write 0xFF then increment RAM address and go to step (a)
HI-3210
MSB
MSB
15 14
X
7
31
6
X
13 12 11 10 9
5
BISTFH
BISTFL
4
3
2
1
LSB
LSB
8
0