th50vsf3681aasb TOSHIBA Semiconductor CORPORATION, th50vsf3681aasb Datasheet
th50vsf3681aasb
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th50vsf3681aasb Summary of contents
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... Erase and Program cycle for flash memory 5 10 SRAM • Boot block architecture for flash memory 524,288 words of 16 bits TH50VSF3680AASB: Top boot block 1,048,576 words of 8 bits TH50VSF3681AASB: Bottom boot block 1,048,576 words of 8 bits • Package P-FBGA69-1209-0.80A3: 0.31 g (typ.) PIN NAMES ...
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PIN ASSIGNMENT (TOP VIEW) • Case: CIOF = V , CIOS = V (×16, × /ACC RESET ...
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BLOCK DIAGRAM A0~A22 WP /ACC RESET CEF CIOF CE2S UB LB CIOS MODE SELECTION OPERATION MODE CEF L Flash Read L H SRAM Read Flash Write L H ...
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... ID CODE TABLE TYPE Manufacturer Code TH50VSF3680AASB Device Code TH50VSF3681AASB Verify Block Protect Note (1) DQ8~DQ15 are Hi-Z in Byte mode (2) BA: Block address (3) 0001H: Protected block 0000H: Unprotected block A21~A12 ( TH50VSF3680/3681AASB A0 CODE (HEX 0098H ...
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... Bank Address and ID Read Address (A6, A1, A0) Bank Address = A21~A15 Manufacturer Code = ( Device Code = ( (5) ID: ID Data 0098H - Manufacturer Code 0093H - Device Code (TH50VSF3680AASB) 0095H - Device Code (TH50VSF3681AASB) 0001H - Protected Block SECOND BUS THIRD BUS WRITE CYCLE WRITE CYCLE Data Addr ...
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BLOCK ERASE ADDRESS TABLES (1) TH50VSF3680AASB (top boot block) BANK BLOCK BANK ADDRESS # # A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA0 L L BA1 L L BA2 L L BA3 L L BK0 BA4 L ...
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BANK BLOCK BANK ADDRESS # # A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA32 BA33 BA34 BA35 BK4 BA36 BA37 L H ...
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BANK BLOCK BANK ADDRESS # # A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA64 BA65 BA66 BA67 BK8 BA68 BA69 H L ...
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BANK BLOCK BANK ADDRESS # # A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA96 BA97 BA98 BA99 BK12 BA100 BA101 H H ...
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BANK BLOCK BANK ADDRESS # # A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA127 BA128 BA129 BA130 BK16 BA131 BA132 H H ...
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... TH50VSF3681AASB (bottom boot block) BANK BLOCK BANK ADDRESS # # A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA0 BA1 BA2 BA3 BK0 BA4 BA5 BA6 BA7 BA8 BA9 BA10 ...
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BANK BLOCK BANK ADDRESS # # A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA31 BA32 BA33 BA34 BK4 BA35 BA36 L L ...
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BANK BLOCK BANK ADDRESS # # A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA63 BA64 BA65 BA66 BK8 BA67 BA68 L H ...
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BANK BLOCK BANK ADDRESS # # A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA95 BA96 BA97 BA98 BK12 BA99 BA100 H L ...
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BANK BLOCK BANK ADDRESS # # A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA127 BA128 BA129 BA130 BK16 BA131 BA132 H H ...
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BLOCK SIZE TABLE (1) TH50VSF3680AASB (top boot block) BLOCK SIZE BLOCK # BYTE MODE BA0~BA7 64 Kbytes BA8~BA15 64 Kbytes BA16~BA23 64 Kbytes BA24~BA31 64 Kbytes BA32~BA39 64 Kbytes BA40~BA47 64 Kbytes BA48~BA55 64 Kbytes BA56~BA63 64 Kbytes BA64~BA71 64 ...
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... TH50VSF3681AASB (bottom boot block) BLOCK SIZE BLOCK # BYTE MODE BA0~BA7 8 Kbytes BA8~BA14 64 Kbytes BA15~BA22 64 Kbytes BA23~BA30 64 Kbytes BA31~BA38 64 Kbytes BA39~BA46 64 Kbytes BA47~BA54 64 Kbytes BA55~BA62 64 Kbytes BA63~BA70 64 Kbytes BA71~BA78 64 Kbytes BA79~BA86 64 Kbytes BA87~BA94 64 Kbytes BA95~BA102 64 Kbytes BA103~BA110 64 Kbytes BA111~BA118 64 Kbytes BA119~BA126 64 Kbytes ...
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ABSOLUTE MAXIMUM RATINGS SYMBOL Supply Voltage CC CCs CCf (1) V Input Voltage IN V Input/Output Voltage DQ T Operating Temperature opr P Power Dissipation D T Soldering Temperature (10 s) solder I Output Short Circuit Current ...
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RECOMMENDED DC OPERATING CONDITIONS SYMBOL V /V Power Supply Voltage CCs CCf V Input High-Level Voltage IH V Input Low-Level Voltage IL V Data Retention Voltage for SRAM DH V Flash Low-Lock Voltage LKO V High Voltage for WP ACC ...
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V DC CHARACTERISTICS SYMBOL PARAMETER I Input Leakage Current IL Input Leakage Current I ILW ( WP /ACC pin) I SRAM Output High Current SOH I SRAM Output Low Current ...
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V AC CHARACTERISTICS Read cycle SYMBOL t Read Cycle Time RC t Address Access Time ACC t Chip Enable ( CO1 t Chip Enable (CE2S) Access ...
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AC CHARACTERISTICS (FLASH MEMORY) READ CYCLE SYMBOL t Read Cycle Time RC t Address Access Time ACC t CEF Access Time Access Time OE t CEF to Output Lo-Z CEE Output Lo-Z OEE t ...
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COMMAND WRITE/PROGRAM/ERASE CYCLE SYMBOL t Command Write Cycle Time CMD t Address Set-up Time / CIOF Set-up Time AS t Address Hold Time / CIOF Hold Time AH t Address Hold Time from WE High level AHW t Data Set-up ...
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SIMULTANEOUS READ/WRITE OPERATION The TH50VSF3680/3681AASB features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation enables the device to simultaneously write data to or erase data from a bank while the device reads data from another bank. The TH50VSF3680/3681AASB has a ...
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ID Read Mode ID Read mode is used to read the device maker code and device code. The mode is useful for EPROM programmers to automatically identify the device type. In this method, simultaneous operation can be performed. Inputting an ...
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Command Write The TH50VSF3680/3681AASB utilizes the JEDEC command control standard for a single power supply 2 E PROM. A Command is executed by inputting an address and data into the Command register. The Command is written by inputting a pulse ...
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Auto-Program Mode The TH50VSF3680/3681AASB can be programmed in either byte or word units. The Auto Program mode is set using the Program command. The program address is latched on the falling edge of the WE signal and data is latched ...
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Program Suspend / Resume Mode Program Suspend is used to enable Data Read by suspending Write operation. The device receives a Program Suspend command in Write mode (including Write performed during Erase Suspend) but ignores the command in other modes. ...
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Auto Block / Multiple Block Erase Mode The Auto Block and Multiple Block Erase modes are set using the Block Erase command. The block address is latched on the falling edge of the WE signal in the sixth bus cycle. ...
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Block Protect Block Protection is a function to disable write and erase in block units. Applying V to RESET and inputting the Block Protect command performs block protection. The first cycle of ID the command sequence is the Setup command. ...
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... To exit Hidden ROM mode, use the Hidden ROM Mode Exit command. The device returns to Read mode. Hidden Rom Area Address Table BOOT BLOCK TYPE ARCHITECTURE TH50VSF3680AASB TOP BOOT BLOCK TH50VSF3681AASB BOTTOM BOOT BLOCK rather than V is input to RESET . Once the block is protected BYTE MODE ...
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Common Flash Memory Interface (CFI) The TH50VSF3680/3681AASB conforms to the CFI. Information on device specifications and characteristics can be obtained via CFI. To read information from the device, input the Query command followed by the address. In Word mode, DQ8 ...
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... Block Protect/Unprotect scheme Simultaneous Operation 0: Not Supported 1: Supported Burst Mode 0: Not Supported Page Mode 0: Not Supported V Min voltage ACC DQ7~DQ4 DQ3~DQ0: 100 mV V Max voltage ACC DQ7~DQ4 DQ3~DQ0: 100 mV Top/Bottom Boot Block Flag 2: TH50VSF3680AASB 3: TH50VSF3681AASB Program Suspend 0: Not Supported 1: Supported 2001-03-06 33/55 ...
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HARDWARE SEQUENCE FLAGS FOR FLASH MEMORY The TH50VSF3680/3681AASB has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation. The output data is read out using the same timing as that used when ...
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DQ3 (Block Erase timer) The Block Erase operation starts 50 µs (Erase Hold Time) after the rising edge the last command cycle. DQ3 outputs a 0 during the Block Erase Hold Time and a 1 when the ...
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DATA PROTECTION The TH50VSF3680/3681AASB features a function which makes malfunction or data damage difficult. Protection Against Program/Erase Caused by Low Supply Voltage To prevent malfunction at power on or power down, the device does not receive commands when V V ...
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TIMING DIAGRAMS FLASH READ/ID READ OPERATION Address CEF OEH D OUT SRAM READ CYCLE (see Note 1) Address CE2S Hi-Z OUT Data Invalid t ...
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SRAM WRITE CYCLE Address CE2S See Note 2 OUT D See Note SRAM WRITE CYCLE 2 ( Address CE2S CE ...
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SRAM WRITE CYCLE 3 (CE2S-CONTROLLED) (see Note 4) Address CE2S OUT D See Note SRAM WRITE CYCLE 4 ( Address CE2S UB ...
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FLASH COMMAND WRITE OPERATION This is the timing of the Command Write Operation. The timing which described follow pages is typically same as this page’s. • WE Control Address CEF • CEF Control Address CEF WE D ...
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FLASH ID READ OPERATION (Input command sequence) Address 555H t CMD CEF OE t OES WE D AAH IN D OUT Read Mode (Input ID Read Command Sequence) (Continued) 555H Address t CMD CEF AAH IN D ...
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FLASH AUTO-PROGRAM OPERATION ( Address 555H t CMD CEF OE t OES WE D AAH IN D OUT t VCS V CCf Note: Word Mode address shown. PA: Program address PD: Program data FLASH AUTO CHIP ERASE/AUTO BLOCK ERASE OPERATION ...
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FLASH AUTO-PROGRAM OPERATION ( 555H Address t CMD CEF OE t OES AAH D OUT t VCS V CCf Notes: Word mode address shown PA: Program address PD: Program data FLASH AUTO CHIP ERASE/AUTO BLOCK ERASE OPERATION ...
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FLASH PROGRAM/ERASE SUSPEND OPERATION Address BK CEF B0H IN D Hi-Z OUT Program/Erase Mode RA: Read address BK: Bank address FLASH PROGRAM/ERASE RESUME OPERATION Address RA CEF OE t OES WE t DF1 t ...
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FLASH DURING AUTO-PROGRAM/ERASE OPERATION CEF FLASH HARDWARE RESET OPERATION WE RESET RESET FLASH READ AFTER Address RESET D OUT Command input sequence READY t RC ...
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FLASH HARDWARE SEQUENCE FLAG ( Last Address Command Address t CMD Last D Command IN Data DQ7 DQ0~DQ6 t BUSY PA: Program address BA: Block address FLASH HARDWARE SEQUENCE FLAG (Toggle Bit) Last Address ...
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FLASH BLOCK PROTECT OPERATION Address t CMD CEF VPS RESET D 60h IN D OUT Notes Block address Next Block address * : 01h ...
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TIMING FOR SWITCHING BETWEEN FLASH AND SRAM MODES CEF CE2S Notes: (1) WE remains High during a Read cycle. ( goes Low (or CE2S goes High) at the same time as or after ...
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SRAM DATA RETENTION CHARACTERISTICS SYMBOL V Data Retention Supply Voltage for SRAM DH I SRAM Standby Current CCS4 t Chip-Deselect-to-Data-Retention-Mode Time CDR t Recovery Time r (1) Read cycle time -CONTROLLED DATA RETENTION MODE (see Note 1) ...
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FLOWCHARTS OF FLASH MEMORY OPERATIONS Auto-Program Address = Address + 1 Note: Word mode command sequence is shown. Start Auto-Program Command Sequence (see below) DATA Polling or Toggle Bit No Last Address? Yes Auto-Program Completed Auto-Program command sequence (address/data) 555H/AAH ...
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Fast Program Address = Address + 1 Fast Program Set command sequence (address/data) 555H/AAH 2AAH/55H 555H/20H TH50VSF3680/3681AASB Start Fast Program Set Command Sequence (see below) Fast Program Command Sequence (see below) DATA Polling or Toggle Bit No Last Address? Yes ...
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Auto-Erase Auto Chip Erase command sequence (address/data) 555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H 555H/10H Note: Word mode command sequence is shown. Start Auto-Erase Command Sequence (see below) DATA Polling or Toggle Bit Auto-Erase Completed Auto Block Erase / Multiple-Block Erase command ...
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DQ7 ( DATA Polling) Start Read Byte (DQ0~DQ7) Addr DQ7 = Data? No DQ5 = 1? Read Byte (DQ0~DQ7) Addr DQ7 = Data? Fail DQ6 (Toggle bit) Start Read Byte (DQ0~DQ7) Addr DQ6 = ...
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Block Protect RESET = V PLSCNT = 1 Block Protect Command First Bus Write Cycle Set up Address Addr. = BPA Block Protect Command Second Bus Write Cycle Wait to 100 µs Block Protect Command Third Bus Write Cycle Verify ...
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PACKAGE DIMENSIONS TH50VSF3680/3681AASB Unit: mm 2001-03-06 55/55 ...