m36l0r7060t1zaqe Numonyx, m36l0r7060t1zaqe Datasheet

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m36l0r7060t1zaqe

Manufacturer Part Number
m36l0r7060t1zaqe
Description
128 Mbit Multiple Bank, Multilevel, Burst Flash Memory And 64 Mbit Burst Psram, 1.8 V Supply, Multichip Package
Manufacturer
Numonyx
Datasheet
Features
Flash memory
November 2007
Multichip package
– 1 die of 128 Mbit (8 Mb x16, Multiple Bank,
– 1 die of 64 Mbit (4 Mb x16) Pseudo SRAM
Supply voltage
– V
– V
Electronic signature
– Manufacturer Code: 20h
– Top Device Code
– Bottom Device Code
Package
– ECOPACK®
Synchronous / Asynchronous Read
– Synchronous Burst Read mode: 54 MHz,
– Random Access: 70 ns, 85 ns
Synchronous Burst Read Suspend
Programming time
– 2.5 µs typical word program time using
Memory organization
– Multiple Bank memory array: 8 Mbit banks
– Parameter Blocks (top or bottom location)
Common Flash Interface (CFI)
100 000 program/erase cycles per block
Dual operations
– program/erase in one Bank while read in
– No delay between read and write
Multilevel, Burst) Flash memory
M36L0R7060T1: 88C4h
M36L0R7060B1: 88C5h
66 MHz
Buffer Enhanced Factory Program
command
others
operations
DDF
PPF
and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package
= 9 V for fast program
= V
CCP
128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory
= V
DDQF
= 1.7 to 1.95 V
Rev 2
PSRAM
Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
– WP
– Absolute Write Protection with V
Access time: 70 ns
Asynchronous Page Read
– Page Size: 4, 8 or 16 words
– Subsequent read within page: 20 ns
Low power features
– Automatic Temperature-compensated Self-
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) mode
Synchronous Burst Read/Write
with zero latency
Refresh (TCR)
F
for Block Lock-Down
M36L0R7060B1
M36L0R7060T1
TFBGA88 (ZAQ)
8 x 10 mm
FBGA
www.numonyx.com
PPF
= V
1/22
SS
1

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m36l0r7060t1zaqe Summary of contents

Page 1

... Asynchronous Page Read – Page Size words – Subsequent read within page ■ Low power features – Automatic Temperature-compensated Self- Refresh (TCR) – Partial Array Self-Refresh (PASR) – Deep Power-Down (DPD) mode ■ Synchronous Burst Read/Write Rev PPF SS 1/22 www.numonyx.com 1 ...

Page 2

Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

M36L0R7060T1, M36L0R7060B1 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

M36L0R7060T1, M36L0R7060B1 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

... It must be read in conjunction with the M58LR128HTB and M69KB096AM datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from your local Numonyx distributor. Recommended operating conditions do not allow more than one memory to be active at the same time. ...

Page 7

M36L0R7060T1, M36L0R7060B1 Table 1. Signal names Signal name A0-A22 Address inputs DQ0-DQ15 Common Data input/output L Latch Enable input for Flash memory and PSRAM K Burst Clock for Flash memory and PSRAM WAIT Wait Data in Burst Mode for Flash ...

Page 8

Description Figure 2. TFBGA connections (top view through package 8/ ...

Page 9

... Flash memory. 2.4 Clock (K) The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AM for the PSRAM and M58LR128HTB for the Flash memory. and Table 1: Signal ...

Page 10

Signal descriptions 2.5 Wait (WAIT) WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of how ...

Page 11

M36L0R7060T1, M36L0R7060B1 2.11 PSRAM Chip Enable input (E The Chip Enable input activates the PSRAM when driven Low (asserted). When de- asserted (V ), the device is disabled, and goes automatically in low-power Standby mode IH or Deep Power-down mode, ...

Page 12

Signal descriptions 2.19 V supply voltage DDQF V provides the power supply for the Flash I/O pins. This allows all outputs to be DDQF powered independently of the Flash core power supplies, V 2.20 V Program supply voltage PPF V ...

Page 13

M36L0R7060T1, M36L0R7060B1 3 Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: E and E for the PSRAM. P Recommended operating conditions do not ...

Page 14

Functional description Table 2. Main operating modes (2)(3) Operation Flash Read Flash Write Flash Address ...

Page 15

... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 3. ...

Page 16

DC and AC parameters 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests ...

Page 17

... Figure 5. AC measurement load circuit Table 5. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Please refer to the M58LR128HTB and M69KB096AM datasheets for further DC and AC characteristics values and illustrations DDF DDQF DEVICE UNDER TEST 0.1µF 0.1µF C ...

Page 18

... Package mechanical 6 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ...

Page 19

M36L0R7060T1, M36L0R7060B1 Table 6. Stacked TFBGA88 8 × × 10 active ball array, 0.8 mm pitch, package mechanical data Symbol Typ 0.850 b 0.350 D 8.000 D1 5.600 ddd E 10.000 E1 7.200 ...

Page 20

... Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 20/22 M36 ZAQ ...

Page 21

... Date 23-May-2006 31-Aug-2006 07-May-2007 13-Nov-2007 Revision 0.1 First release. PSRAM changed to M69KM096AM. Blank and T removed below 0.2 Option in Table 7: Ordering information Document status promoted from Target Specification to full Datasheet speed class and 66 MHz frequency added. 2 Applied Numonyx branding. Revision history Changes scheme. 21/22 ...

Page 22

... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...

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