am49lv6408m Meet Spansion Inc., am49lv6408m Datasheet
am49lv6408m
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am49lv6408m Summary of contents
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Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these ...
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... ADVANCE INFORMATION Am49LV6408M Stacked Multi-chip Package (MCP) 64 Mbit ( bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High Performance — Access time as fast as 100ns initial 5 ns page Flash 55 ns pSRAM Package — ...
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... The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. Am49LV6408M November 5, 2003 ...
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... Figure 28. Pseudo SRAM Write Cycle—WE# Control ................... 56 Figure 29. Pseudo SRAM Write Cycle—CE1#s Control ................ 57 Flash Erase And Programming Performance . . 58 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 58 BGA Package Capacitance . . . . . . . . . . . . . . . . . 58 Data Retention Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 60 TLB069—69-Ball Fine-pitch Ball Grid Array (FBGA Package ................................................................ 60 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61 Am49LV6408M 3 ...
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... Flash Memory = 2.7–3 100 100 RY/BY Bit Flash Memory DQ15 to DQ0 V s CCQ SS SSQ 8 M Bit DQ15 to DQ0 pseudo Static RAM Am49LV6408M Am49LV6408M pSRAM 11 15 10, 11 110 55 70 110 N/A N DQ15 to DQ0 November 5, 2003 ...
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... Register CE#f OE# V Detector CC A21–A0 November 5, 2003 Sector Switches Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Logic Y-Decoder STB Timer X-Decoder Am49LV6408M – DQ15 DQ0 Input/Output Buffers Data STB Latch Y-Gating Cell Matrix 5 ...
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... DQ12 DQ7 DQ11 NC DQ5 DQ14 integrity may be compromised if the package body is exposed to temperatures about 150 periods of time. Am49LV6408M Flash only A10 NC pSRAM only Shared C9 A15 D9 A21 E9 E10 F10 A16 K10 NC ° ...
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... pSRAM Power Supply Device Ground Pin Not Connected Internally UB#ps = Upper Byte Control (pSRAM) LB#ps = Lower Byte Control (pSRAM) November 5, 2003 LOGIC SYMBOL 22 A21–A0 DQ15–DQ0 CE1#ps CE2ps OE# WE# WP#/ACC RESET#f UB#ps LB#ps Am49LV6408M 16 RY/BY# 7 ...
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... Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM Am29LV640M 64 Megabit ( 16-Bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM Valid Combinations Order Number Am49LV6408MT15I Am49LV6408MB15I Am49LV6408MT10I T Am49LV6408MB10I Am49LV6408MT11I Am49LV6408MB11I TAPE AND REEL inches ...
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... The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am49LV6408M 9 ...
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... 11.5–12 9.0 ± 0 Don’t Care, SADD = Flash Sector Data Out OUT and CE2ps = V at the same time the boot sectors protection will be removed. IH Am49LV6408M WP#/ACC DQ7– DQ15– (Note 4) DQ0 X H L/H D OUT X H (Note ± ...
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... The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V (Note that this is a more restricted voltage range than CE# and RESET# are held Am49LV6408M 3 and 2 indicates the AC Char- section contains timing specification tables ...
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... Am49LV6408M ±0.3 V, the device RESET# is held CC4 ±0.3 V, the standby current will SS AC Characteristics tables for RESET# pa- , output from the device is IH (x16) Address Range 00000h–07FFFh 08000h–0FFFFh 10000h–17FFFh 18000h–1FFFFh 20000h– ...
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... Am49LV6408M (x16) Address Range C8000h–CFFFFh D0000h–D7FFFh D8000h–DFFFFh E0000h–E7FFFh E8000h–EFFFFh F0000h–F7FFFh F8000h–FFFFFh F9000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h– ...
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... Am49LV6408M (x16) Address Range 280000h–28FFFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2FFFFFh 2F8000h– ...
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... Am49LV6408M (x16) Address Range 00000h–00FFFh 01000h–01FFFh 02000h–02FFFh 03000h–03FFFh 04000h–04FFFh 05000h–05FFFh 06000h–06FFFh 07000h–07FFFh 08000h–0FFFFh 10000h–17FFFh 18000h–1FFFFh 20000h–27FFFh 28000h–2FFFFh 30000h–37FFFh 38000h–3FFFFh 40000h– ...
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... Am49LV6408M (x16) Address Range 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h– ...
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... Am49LV6408M (x16) Address Range 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h– ...
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... SA31-SA34 256 (4x64) Kbytes SA35-SA38 256 (4x64) Kbytes SA39-SA42 256 (4x64) Kbytes SA43-SA46 256 (4x64) Kbytes SA47-SA50 256 (4x64) Kbytes SA51-SA54 Am49LV6408M Sector/ A21–A12 Sector Block Size 10100XXXXX 256 (4x64) Kbytes 10101XXXXX 256 (4x64) Kbytes 10110XXXXX 256 (4x64) Kbytes 10111XXXXX ...
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... Kbytes 256 (4x64) Kbytes Notes: 1. All protected sector groups unprotected (If WP the first or last sector will remain protected). 2. All previously protected sector groups are protected once again. Figure 1. Temporary Sector Group Am49LV6408M V . During this mode, for- ID START RESET (Note 1) ...
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... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Group Unprotect Algorithm Am49LV6408M START PLSCNT = 1 RESET Wait 1 µs Temporary Sector No First Write Group Unprotect Cycle = 60h? Mode Yes All sector No groups ...
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... To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is programmed, locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing within the remainder of the array. Am49LV6408M Table 6 for Command Definitions ...
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... For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Al- ternatively, contact an AMD representative for copies of these documents. Am49LV6408M , the device does not ac- LKO is greater than V CC LKO ...
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... Description Min. (write/erase) Max. (write/erase) Min. voltage (00h = no V pin present) PP Max. voltage (00h = no V pin present (00h = not supported) N times typical N times typical N N times typical (00h = not supported) Am49LV6408M N µs µ s (00h = not supported times typical 23 ...
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... Erase Block Region 3 Information (refer to CFI publication 100) 37h 0000h 38h 0000h 39h 0000h 3Ah 0000h Erase Block Region 4 Information (refer to CFI publication 100) 3Bh 0000h 3Ch 0000h Table 9. Device Geometry Definition Description N byte N Am49LV6408M November 5, 2003 ...
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... Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after Am49LV6408M section for timing 25 ...
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... The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides Am49LV6408M A7:A0 Identifier Code (x16) Manufacturer ID 00h ...
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... Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. Am49LV6408M –A . All subsequent ad- MAX ...
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... In addition, no external pullup is nec- essary since the WP#/ACC pin has internal pullup Figure 5 illustrates the algorithm for the program oper- ation. Refer to the table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams. Am49LV6408M for operations HH Erase and Program Operations November 5, 2003 ...
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... Yes No 4. Yes Yes No PASS Am49LV6408M When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. Therefore, DQ7 should be verified. DQ5= “1”, then the device FAILED. If this flowchart location was reached because DQ1= “ ...
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... Program Suspend mode and continue the programming opera- tion. Further writes of the Resume command are ig- nored. Another Program Suspend command can be written after the device has resume programming. Am49LV6408M Write Operation Status for more November 5, 2003 ...
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... The system must rewrite the command se- quence and any additional addresses and commands. The system can monitor DQ3 to determine if the sec- tor erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris- Am49LV6408M section for infor- ta- 11 and ...
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... Further writes of the Resume com- mand are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Am49LV6408M Write Operation Status section for infor- Write Operation Status section for more and sections for details ...
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... The Erase Suspend command is valid only during a sector erase operation. 16. The Erase Resume command is valid only during the Erase Suspend mode. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. Am49LV6408M Fourth Fifth Sixth Addr Data Addr ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 8. Data# Polling Algorithm Am49LV6408M section shows the Data# Yes Yes PASS November 5, 2003 ...
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... Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences be- tween DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit Am49LV6408M II. 35 ...
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... DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. Alternatively, it may choose to perform Am49LV6408M Table 12 to compare out- RY/BY#: Ready/Busy# sub- ...
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... DQ7# Toggle 0 0 Toggle 0 Invalid (not allowed) Data 1 No toggle 0 Data DQ7# Toggle 0 DQ7# Toggle 0 DQ7# Toggle 0 Am49LV6408M Sector Erase Command Write Buffer DQ2 DQ3 (Note 2) DQ1 RY/BY# N/A No toggle Toggle N ...
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... Note: Operating ranges define those limits between which the functionality of the device is guaranteed +0.8 V –0.5 V –2.0 V Figure 10 +0 –2.0 V for SS Figure 11. Am49LV6408M Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform November 5, 2003 ...
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... CC min < maximum minimum V CC for these connections voltage requirements max voltage requirements Includes RY/BY# 10. Not 100% tested. Am49LV6408M Min Typ Max ±1 ±1 ...
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... IH IL CE1#s=V , CE2 IL: Other inputs = IL 85° 3 CE1#s=V , CE2 IL: Other inputs = IL 85° 3 ns. Am49LV6408M Min Typ Max –1.0 1.0 –1.0 1 –0.2 0.4 (Note 3) V +0.2 CC 2.2 (Note 2) 0.4 2.2 0 November 5, 2003 Unit µ ...
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... Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am49LV6408M All Speeds Unit 1 TTL gate 0.0–3 ...
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... Test Setup CE Read Toggle and Data# Polling t RC Addresses Stable t ACC OEH t CE HIGH Z Figure 14. Read Operation Timings Am49LV6408M Speed 10 Min 100 110 Max 100 110 IL Max 100 110 Max 35 40 Max 35 40 Max 16 Max 16 ...
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... CHARACTERISTICS A21-A2 A1-A0 Data Bus CE#f OE# November 5, 2003 Same Page PACC PACC t ACC Qa Qb Figure 15. Page Read Timings Am49LV6408M PACC ...
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... Description Max Max Min Min Min Min = V . Contact AMD for information on AC operation with Reset Timings during Embedded Algorithms t RP Figure 16. Reset Timings Am49LV6408M All Speed Options Unit 20 ms 500 ns 500 µ ¼ ...
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... Min Min Min Min Min Min Min Min Min Min Min Typ Per Word Typ Per Word Typ Word Typ Word Typ Typ Min Min Min Am49LV6408M Speed Options 10 Unit 100 110 ...
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... WPH A0h is the true data at the program address. OUT Figure 17. Program Operation Timings Am49LV6408M Read Status Data (last two cycles WHWH1 Status D OUT VHH November 5, 2003 ...
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... SA = sector address (for Sector Erase Valid Address for reading status data (see “Write Operation Status”. 2. Illustration shows device in word mode. Figure 19. Chip/Sector Erase Operation Timings November 5, 2003 555h for chip erase WPH t DH 55h 30h 10 for Chip Erase Am49LV6408M Read Status Data WHWH2 In Complete Progress 47 ...
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... Notes:Note Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle Complement Complement True Status Data Status Data True Figure 20. Data# Polling Timings (During Embedded Algorithms) Am49LV6408M VA High Z Valid Data High Z Valid Data November 5, 2003 ...
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... AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 22. DQ2 vs. DQ6 Am49LV6408M Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read 49 ...
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... VIDR CE#f WE# Figure 23. Temporary Sector Group Unprotect Timing Diagram Min Min Program or Erase Command Sequence t RSP Am49LV6408M All Speed Options Unit 500 ns 4 µ VIDR November 5, 2003 ...
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... Note: For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010. Figure 24. Sector Group Protect and Unprotect Timing Diagram November 5, 2003 Valid* Valid* Verify 60h 40h Sector Group Protect: 150 µs, Sector Group Unprotect Am49LV6408M Valid* Status 51 ...
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... Min Min Min Min Min Min Min Min Min Min Typ Per Word Typ Per Word Typ Word Typ Word Typ Typ Min Am49LV6408M Speed Options 10 Unit 100 110 ...
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... SA for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Operation Timings Am49LV6408M PA DQ7# D OUT 53 ...
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... CE#1ps Min Max Max Max Max Min Min Min Max Max Max Min UB#ps and/or LB# for continuous periods < 10 µs. RC Am49LV6408M . IH Speed Unit 15 10 ...
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... CO1 t CO2 OLZ t BLZ t LZ (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ for continuous periods < 10 µs. RC Figure 27. Pseudo SRAM Read Cycle Am49LV6408M BHZ t OHZ Data Valid 55 ...
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... WP (See Note (See Note 3) High-Z t WHZ Data Undefined applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am49LV6408M Speed Unit ...
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... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low Am49LV6408M t (See Note Data Valid High-Z is measured from the beginning of write ...
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... Word 17 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 = 3.0 V, one pin at a time. CC Test Setup OUT Am49LV6408M Unit Comments sec sec µs µs µs µs µs µs sec . Programming specifications assume CC 12 Min Max – ...
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... DATA RETENTION Parameter Description Minimum Pattern Data Retention Time November 5, 2003 Test Conditions 150°C 125°C Am49LV6408M Min Unit 10 Years 20 Years 59 ...
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... IN THE OUTER ROW E/2 BALL PITCH 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. SOLDER BALL PLACEMENT 9. NOT USED. DEPOPULATED SOLDER BALLS 10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. Am49LV6408M ...
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... AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. November 5, 2003 Am49LV6408M 61 ...