k4t1g084qa-zce60 Samsung Semiconductor, Inc., k4t1g084qa-zce60 Datasheet - Page 27
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k4t1g084qa-zce60
Manufacturer Part Number
k4t1g084qa-zce60
Description
1gb A-die Ddr2 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4T1G084QA-ZCE60.pdf
(28 pages)
1G A-die DDR2 SDRAM
31. Input waveform timing is referenced from the input signal crossing at the V
device under test.
32. Input waverorm timing is referenced from the input signal crossing at the V
device under test.
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the sin-
gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be mono-
tonic between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be mono-
tonic between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registeration. Thus, after any CKE transition, CKE may not change from its valid level during the time period of tIS
+ 2*tCK + tIH.
CK
CK
tIS
tIH
Page 27 of 28
IH(ac)
IL(dc)
tIS
) level for a rising signal and V
level for a rising signal and V
tIH
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
IL(ac)
IH
(dc) for a falling signal applied to the
for a falling signal applied to the
max
max
min
min
DDR2 SDRAM
Rev. 1.1 Aug. 2005