k4t51163qi-hpf7 Samsung Semiconductor, Inc., k4t51163qi-hpf7 Datasheet - Page 24
![no-image](/images/no-image-200.jpg)
k4t51163qi-hpf7
Manufacturer Part Number
k4t51163qi-hpf7
Description
512mb I-die Ddr2 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4T51163QI-HPF7.pdf
(42 pages)
- Current page: 24 of 42
- Download datasheet (810Kb)
K4T51163QI
DQS
Note1
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
V
V
V
V
Setup Slew Rate
V
V
IL(dc)
Falling Signal
REF(dc)
IL(ac)
DDQ
IH(dc)
IH(ac)
Figure 6 - Illustration of nominal slew rate for tDS (single-ended DQS)
max
max
V
V
V
V
V
V
V
min
min
V
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
SS
max
max
min
min
VREF to ac
region
=
V
∆TF
REF(dc)
- Vil(ac)max
∆TF
nominal slew
tDS
rate
24 of 42
tDH
Setup Slew Rate
Rising Signal
∆TR
tDS
nominal
slew rate
=
Industrial
Vih(ac)min - V
tDH
VREF to ac
region
∆TR
REF(dc)
Rev. 1.0 August 2009
DDR2 SDRAM
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