k4s640832e-tl75 Samsung Semiconductor, Inc., k4s640832e-tl75 Datasheet
k4s640832e-tl75
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k4s640832e-tl75 Summary of contents
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M366S1623ET0 Revision History Revision 0.0 (Dec, 2000) • PC133 first published. PC133 Unbuffered DIMM REV. 0.0 Dec, 2000 ...
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... M366S1623ET0 M366S1623ET0 SDRAM DIMM 16Mx64 SDRAM DIMM based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung M366S1623ET0 is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M366S1623ET0 consists of sixteen CMOS bit with 4banks ...
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M366S1623ET0 PIN CONFIGURATION DESCRIPTION Pin Name CLK System clock CS Chip select CKE Clock enable A0 ~ A11 Address BA0 ~ BA1 Bank select address RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 Data ...
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... DQ30 DQ6 DQ31 DQ7 A0 ~ An, BA0 & 1 SDRAM U0 ~ U15 SDRAM U0 ~ U15 RAS CAS SDRAM U0 ~ U15 SDRAM U0 ~ U15 WE CKE0 SDRAM DQn Every DQpin of SDRAM V DD Two 0.1uF Capacitors per each SDRAM Vss DQM4 DQM CS DQ0 DQ32 DQ33 DQ1 DQ34 DQ2 U8 DQ3 ...
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M366S1623ET0 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. ...
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M366S1623ET0 DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T Parameter Symbol Operating current I CC1 (one Bank Active Precharge standby current in CC2 power-down mode I PS CC2 I N CC2 Precharge standby current in non power-down ...
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M366S1623ET0 AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V 1200 Output 50pF 870 (Fig output load circuit OPERATING ...
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M366S1623ET0 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter CLK cycle time CAS latency=3 CLK to valid CAS latency=3 output delay Output data CAS latency=3 hold time CLK high pulse ...
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... MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...
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... Detail A Tolerances : 0.005(.13) unless otherwise specified The used device is 8Mx8 SDRAM, TSOP SDRAM Part No. : K4S640832E-TC75 5.250 (133.350) 5.014 (127.350 0.250 0.250 (6.350) (6.350) 1.450 2.150 (36.830) (54.61) 4 ...
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... M366S1623ET0 M366S1623ET0-C75(Intel SPD 1.2B ver. base) Organization : 16Mx64 ¡Ü Composition : 8Mx8 *16 ¡Ü Used component part # : K4S640832E-TC75 ¡Ü rows in module : 2 rows ¡Ü banks in component : 4 banks ¡Ü Feature : 1,375mil height & double sided component ¡Ü Refresh : 4K/64ms ¡Ü ...
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M366S1623ET0 Byte # Function Described 35 Data signal input hold time 36 Superset information (maybe used in future) 37~60 Superset information (maybe used in future) 61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for ...