k4s560832e-nl75 Samsung Semiconductor, Inc., k4s560832e-nl75 Datasheet - Page 3

• Manufacturer Part Number: k4s560832e-nl75
• Description: 256mb E-die Sdram Specification 54pin Stsop-ii
• Manufacturer: Samsung Semiconductor, Inc.

SDRAM 256Mb E-die (x4, x8)
SDRAM 256Mb E-die (x4, x8
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8)
• Auto & self refresh
• 64ms refresh period (8K Cycle)
GENERAL DESCRIPTION
4bits / 4 x 8,388,608 words by 8bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows pre-
cise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, pro-
grammable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
Ordering Information
The K4S560432E / K4S560832E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
K4S560432E-NC(L)75
K4S560832E-NC(L)75
Part No.
Organization
64Mx4
32Mx8
Row & Column address configuration
Orgainization
64M x 4
32M x 8
Row Address
A0~A12
A0~A12
Max Freq.
133MHz
133MHz
Column Address
A0-A9, A11
A0-A9
Interface
LVTTL
LVTTL
Rev. 1.1 February, 2004
CMOS SDRAM
54pin sTSOP
54pin sTSOP
Package