k4s561632a Samsung Semiconductor, Inc., k4s561632a Datasheet
k4s561632a
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k4s561632a Summary of contents
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... K4S561632A 256Mbit SDRAM 4M x 16bit x 4 Banks * Samsung Electronics reserves the right to change products or specification without notice. Synchronous DRAM LVTTL Revision 0.0 Sep. 1999 CMOS SDRAM Rev. 0.0 Sep. 1999 ...
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... CS * Samsung Electronics reserves the right to change products or specification without notice. GENERAL DESCRIPTION The K4S561632A is 268,435,456 bits synchronous high data rate Dynamic RAM organized 4,196,304 words by 16 bits, fabri- cated with SAMSUNG's high performance CMOS technology. Syn- chronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle ...
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... K4S561632A PIN CONFIGURATION (Top view) A10/AP PIN FUNCTION DESCRIPTION Pin Name CLK System cock CS Chip select CKE Clock enable Address Bank select address 0 1 RAS Row address strobe CAS Column address strobe WE Write enable L(U)DQM Data input/output mask ...
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... K4S561632A ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. ...
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... Operating current I CC4 (Burst mode) Refresh current I CC5 Self refresh current I CC6 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S561632A-TC** 4. K4S561632A-TL** 5. Unless otherwise noticed, input swing level is CMOS Test Condition Burst length = (min CKE ...
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... K4S561632A AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V 1200 Output 50pF 870 (Fig output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) ...
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... K4S561632A AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS latency=3 CLK cycle time CAS latency=2 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=3 Output data hold time CAS latency=2 CLK high pulse width CLK low pulse width Input setup time ...
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... K4S561632A IBIS SPECIFICATION I Characteristics (Pull-up) OH 100MHz 100MHz Voltage Min Max (V) I (mA) I (mA) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 2.6 -21.1 -129.2 2.4 -34.1 -153.3 2.0 -58.7 -197.0 1.8 -67.3 -226.2 1.65 -73.0 -248.0 1.5 -77.9 -269.7 1.4 -80.8 -284.3 1.0 -88.6 -344.5 0.0 -93.0 -502.4 I Characteristics (Pull-down) OL 100MHz 100MHz Voltage Min Max (V) I (mA) I (mA) 0.0 0.0 0.0 0.4 27.5 70.2 0.65 41.8 107.5 0.85 51.6 133.8 1.0 58.0 151.2 1.4 70.7 187.7 1.5 72.9 194.4 1.65 75.4 202.5 1.8 77.0 208.6 1.95 77.6 212.0 3.0 80.3 219.6 3.45 81.4 222.6 66MHz and 100MHz Pull- ...
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... K4S561632A V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) DD 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) SS -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 CMOS SDRAM Minimum V clamp current DD (Referenced Voltage I (mA) Minimum V clamp current -10 -20 -30 -40 -50 -60 Voltage I (mA) Rev ...
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... K4S561632A SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Entry Refresh Self refresh Exit Bank active & row addr. Read & Auto precharge disable column address Auto precharge enable Write & Auto precharge disable column address Auto precharge enable ...