k4s561632a Samsung Semiconductor, Inc., k4s561632a Datasheet - Page 7
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k4s561632a
Manufacturer Part Number
k4s561632a
Description
256mbit Sdram 4m X 16bit X 4 Banks Synchronous Dram Lvttl
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4S561632A.pdf
(10 pages)
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AC CHARACTERISTICS
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
K4S561632A
Notes :
Notes :
CLK cycle time
CLK to valid
output delay
Output data
hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
Output rise time
Output fall time
Output rise time
Output fall time
Parameter
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
1. Rise time specification based on 0pF + 50
2. Fall time specification based on 0pF + 50
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to V
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
Symbol
trh
tfh
trh
tfh
(AC operating conditions unless otherwise noted)
Symbol
t
t
t
t
t
t
t
SAC
t
t
SHZ
SLZ
CC
OH
CH
SH
CL
SS
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Condition
Min
7.5
2.7
2.5
2.5
1.5
0.8
SS
1
-
-
.
to V
-75
to V
DD
1000
Max
SS
5.4
5.4
-
-
, use these values to design to.
, use these values to design to.
Min
8
3
3
3
2
1
1
-
-
1.37
1.30
Min
2.8
2.0
-80
1000
Max
6
6
-
-
Typ
3.9
2.9
Min
10
10
3
3
3
3
2
1
1
-1H
1000
Max
6
6
6
6
Max
4.37
3.8
5.6
5.0
Min
10
12
3
3
3
3
2
1
1
Rev. 0.0 Sep. 1999
CMOS SDRAM
-1L
1000
Volts/ns
Volts/ns
Volts/ns
Volts/ns
Max
6
7
6
7
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1,2
1,2
Note
3
3
1,2
1
2
3
3
3
3
2