k4s561632e Samsung Semiconductor, Inc., k4s561632e Datasheet

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k4s561632e

Manufacturer Part Number
k4s561632e
Description
Ic,sdram,4x4mx16,cmos,tssop,54pin,plastic
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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SDRAM 256Mb E-die (x4, x8, x16)
SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
256Mb E-die SDRAM Specification
54pin sTSOP-II
Revision 1.0
August. 2003
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 August, 2003

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k4s561632e Summary of contents

Page 1

... SDRAM 256Mb E-die (x4, x8, x16) SDRAM 256Mb E-die (x4, x8, x16) 256Mb E-die SDRAM Specification * Samsung Electronics reserves the right to change products or specification without notice. 54pin sTSOP-II Revision 1.0 August. 2003 CMOS SDRAM Rev. 1.0 August, 2003 ...

Page 2

... SDRAM 256Mb E-die (x4, x8, x16) SDRAM 256Mb E-die (x4, x8, x16) Revision History Revision 1.0 (August. 2003) - First release. CMOS SDRAM Rev. 1.0 August, 2003 ...

Page 3

... Cycle) GENERAL DESCRIPTION The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized 16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchro- nous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of oper- ating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications ...

Page 4

... SDRAM 256Mb E-die (x4, x8, x16) SDRAM 256Mb E-die (x4, x8, x16) Package Physical Dimension 54pin sTSOP(II)-300 #54 (1.00) #1 (0.50) NOTE REFERENCE ASS’Y OUT QUALITY #28 (∅ 2.00 Dp0~0.05 BTM) #27 14.40MAX (14.20) ° 14.00±0.10 (14 ) +0.075 0.50TYP 0.20 -0.035 0.50±0.05 ° ( 0.07 MAX CMOS SDRAM Units : Millimeters (2-R 0 ...

Page 5

... SDRAM 256Mb E-die (x4, x8, x16) SDRAM 256Mb E-die (x4, x8, x16) FUNCTIONAL BLOCK DIAGRAM Bank Select CLK ADD LCKE LRAS LCBR CLK CKE * Samsung Electronics reserves the right to change products or specification without notice. Data Input Register 16M 16M ...

Page 6

... SDRAM 256Mb E-die (x4, x8, x16) SDRAM 256Mb E-die (x4, x8, x16) PIN CONFIGURATION (Top view) x16 x8 x4 VDD VDD VDD DQ0 DQ0 NC VDDQ VDDQ VDDQ DQ1 NC NC DQ2 DQ1 DQ0 VSSQ VSSQ VSSQ DQ3 NC NC DQ4 DQ2 NC VDDQ VDDQ VDDQ DQ5 NC NC ...

Page 7

... SDRAM 256Mb E-die (x4, x8, x16) SDRAM 256Mb E-die (x4, x8, x16) ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. ...

Page 8

... SDRAM 256Mb E-die (x4, x8, x16) SDRAM 256Mb E-die (x4, x8, x16) DC CHARACTERISTICS (x4, x8) (Recommended operating condition unless otherwise noted, T Parameter Symbol Operating current I CC1 (One bank active) I CC2 Precharge standby current in PS CKE & CLK ≤ V power-down mode I CC2 I CC2 Precharge standby current in ...

Page 9

... Operating current I CC4 (Burst mode) Refresh current I CC5 Self refresh current I CC6 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S561632E-NC75 4. K4S561632E-NL75 5. Unless otherwise noticed, input swing level is CMOS 70°C) A Test Condition Burst length = 1 ≥ (min ≤ ...

Page 10

... SDRAM 256Mb E-die (x4, x8, x16) SDRAM 256Mb E-die (x4, x8, x16) AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Output 870Ω (Fig output load circuit ...

Page 11

... SDRAM 256Mb E-die (x4, x8, x16) SDRAM 256Mb E-die (x4, x8, x16) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CLK cycle time CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time ...

Page 12

... SDRAM 256Mb E-die (x4, x8, x16) SDRAM 256Mb E-die (x4, x8, x16) IBIS SPECIFICATION I Characteristics (Pull-up) OH 100MHz 100MHz Voltage 133MHz 133MHz Min Max (V) I (mA) I (mA) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 2.6 -21.1 -129.2 2.4 -34.1 -153.3 2.0 -58.7 -197.0 1.8 -67.3 -226.2 1.65 -73.0 -248.0 1.5 -77.9 -269.7 1.4 -80.8 -284.3 1.0 -88.6 -344.5 0.0 -93.0 -502.4 I Characteristics (Pull-down) OL 100MHz 100MHz Voltage 133MHz 133MHz Min Max ...

Page 13

... SDRAM 256Mb E-die (x4, x8, x16) SDRAM 256Mb E-die (x4, x8, x16) V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) DD 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) SS -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 Minimum V clamp current DD (Referenced Voltage I (mA) Minimum V clamp current ...

Page 14

... MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...

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