k4s561632e Samsung Semiconductor, Inc., k4s561632e Datasheet - Page 6

• Manufacturer Part Number: k4s561632e
• Description: Ic,sdram,4x4mx16,cmos,tssop,54pin,plastic
• Manufacturer: Samsung Semiconductor, Inc.

PIN CONFIGURATION (Top view)
SDRAM 256Mb E-die (x4, x8, x16)
SDRAM 256Mb E-die (x4, x8, x16)
PIN FUNCTION DESCRIPTION
CLK
CS
CKE
A
BA
RAS
CAS
WE
DQM
DQ
V
V
N.C/RFU
0
DD
DDQ
~ A
0
0
/V
~ BA
~
Pin
/V
SS
12
N
SSQ
1
System clock
Chip select
Clock enable
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No connection
/reserved for future use
AP/A10
x16
VDDQ
VDDQ
LDQM
VSSQ
VSSQ
VDD
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CAS
RAS
BA0
BA1
WE
CS
A0
A1
A2
A3
AP/A10
VDDQ
VDDQ
VSSQ
VSSQ
x8
VDD
VDD
VDD
DQ0
DQ1
DQ2
DQ3
CAS
RAS
BA0
BA1
Name
WE
NC
NC
NC
NC
NC
CS
A0
A1
A2
A3
AP/A10
VDDQ
VDDQ
VSSQ
VSSQ
x4
VDD
VDD
VDD
DQ0
DQ1
CAS
RAS
BA0
BA1
WE
NC
NC
NC
NC
NC
NC
NC
CS
A0
A1
A2
A3
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
24
25
26
27
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
Column address : (x4 : CA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
0
(7.62mm x 14.00mm)
54 PIN sTSOP(II)
(0.5 mm pin pitch)
~
300mil x 551mil
3
),
(x8 : DQ
0
~ RA
12
SHZ
0
0
,
~
~ CA
7
after the clock and masks the output.
),
9
(x16 : DQ
,CA
Input Function
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
11
), (x8 : CA
0
~
15
x4
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
)
0
Rev. 1.0 August, 2003
~ CA
x8
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
9
), (x16 : CA
CMOS SDRAM
x16
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
0
~ CA
8
)