k4s561633f Samsung Semiconductor, Inc., k4s561633f Datasheet - Page 9
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k4s561633f
Manufacturer Part Number
k4s561633f
Description
4m X 16bit X 4 Banks Mobile Sdram In 54boc
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4S561633F.pdf
(12 pages)
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SIMPLIFIED TRUTH TABLE
NOTES :
1. OP Code : Operand Code
2. MRS can be issued only at all banks precharge state.
3. Auto refresh functions are the same as CBR refresh of DRAM.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation,
K4S561633F - X(Z)E/N/G/C/L/F
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down
Mode
DQM
No Operation Command
it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@MRS)
A new command can be issued after 2 CLK cycles of MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
COMMAND
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
All Banks
Entry
Entry
Entry
Exit
Exit
Exit
CKEn-1 CKEn
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
X
X
X
X
X
X
X
L
L
L
CS
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
RAS
X
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
CAS
H
H
H
H
H
H
X
X
V
X
X
X
V
X
L
L
L
L
WE
H
H
H
H
H
H
L
X
L
L
L
X
V
X
X
X
V
X
(V=Valid, X=Don t Care, H=Logic High, L=Logic Low)
DQM BA0,1 A10/AP
X
X
X
X
X
X
X
X
X
X
X
X
V
X
V
V
V
V
X
Mobile-SDRAM
OP CODE
H
H
H
Row Address
L
L
L
X
X
X
X
X
X
X
A12, A11
A9 ~ A0
(A0~A8)
(A0~A8)
Address
Address
Column
Column
February 2004
X
Note
1, 2
4, 5
4, 5
3
3
3
3
4
4
6
7