ic42s16101-7tig ETC-unknow, ic42s16101-7tig Datasheet - Page 29

• Manufacturer Part Number: ic42s16101-7tig
• Description: 512k X 16 Bit X 2 Banks 16-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16101
Integrated Circuit Solution Inc.
DR025-0F 01/17/2005
Interval Between Read and Write Commands
A read command can be interrupted and a new write
command executed while the read cycle is in progress, i.
e., before that cycle completes. Data corresponding to the
new write command can be input at the point new write
command is executed. To prevent collision between input
and output data at the I/On pins during this operation, the
CAS latency = 2, 3, burst length = 4
COMMAND
U/LDQM
CLK
I/O
READ (CA=A, BANK 0)
READ A0
HI-Z
D
WRITE B0
IN
t
CCD
B0
WRITE (CA=B, BANK 0)
D
IN
B1
D
IN
B2
output data must be masked using the U/LDQM pins. The
interval (t
one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
IN
CCD
B3
) between these commands must be at least
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