m69ar048b STMicroelectronics, m69ar048b Datasheet - Page 4

• Manufacturer Part Number: m69ar048b
• Description: 32 Mbit 2mb X16 1.8v Asynchronous Psram
• Manufacturer: STMicroelectronics

M69AR048B
SUMMARY DESCRIPTION
The M69AR048B is a 32 Mbit (33,554,432 bit)
CMOS memory, organized as 2,097,152 words by
16 bits, and is supplied by a single 1.65V to 1.95V
supply voltage range.
M69AR048B is a member of STMicroelectronics
1T/1C (one transistor per cell) memory family.
These devices are manufactured using dynamic
random access memory cells, to minimize the cell
size, and maximize the amount of memory that
can be implemented in a given area.
However, through the use of internal control logic,
the device is fully static in its operation, requiring
no external clocks or timing strobes, and has a
standard Asynchronous SRAM Interface.
The internal control logic of the M69AR048B han-
dles the periodic refresh cycle, automatically, and
without user involvement.
Figure 2. Logic Diagram
4/29
A0-A20
UB
E1
E2
LB
W
G
21
M69AR048B
V CC
V SS
16
DQ0-DQ15
AI08154
Write cycles can be performed on a single Byte by
using Upper Byte Enable (UB) and Lower Byte En-
able (LB).
The device can be put into standby mode using
Chip Enable (E1) or in Power-Down mode by us-
ing Chip Enable (E2).
The device features several Power-Down modes,
making of power saving a user configurable op-
tion:
Table 1. Signal Names
A0-A20
DQ0-DQ15
E1, E2
G
W
UB
LB
V
V
NC
CC
SS
Partial Power-Down (4 Mbits, 8 Mbits or 16
Mbits) performs a limited refresh of the part of
the PSRAM array that contains essential data.
Deep Power-Down achieves a very low
current consumption by halting all the internal
activities. Since the refresh circuitry is halted,
the duration of the power-down should be less
than the maximum period for refresh.
Address Input
Data Input/Output
Chip Enable, Power-Down
Output Enable
Write Enable
Upper Byte Enable
Lower Byte Enable
Supply Voltage
Ground
Not Connected
(no internal connection)