m69ar048b STMicroelectronics, m69ar048b Datasheet - Page 8

• Manufacturer Part Number: m69ar048b
• Description: 32 Mbit 2mb X16 1.8v Asynchronous Psram
• Manufacturer: STMicroelectronics

M69AR048B
OPERATION
Operational modes are determined by device con-
trol inputs W, E1, E2, LB and UB as summarized
in the
Power Up Sequence
Because the internal control logic of the
M69AR048B needs to be initialized, the following
power-up procedure must be followed before the
memory is used (see
AC
Read Mode
The device is in Read mode when:
The time taken to enter Read mode (t
or t
was the last to reach the appropriate level.
Data out (DQ15-DQ0) may be indeterminate
during t
be valid during t
12
for details of when the outputs become valid.
Write Mode
The device is in Write mode when
The Write cycle begins just after the event (the fall-
ing edge) that causes the last of these conditions
to become true (t
The Write cycle is terminated by the rising edge of
Write Enable (W) or Chip Enable (E1), whichever
occurs first.
If the device is in Write mode (Chip Enable (E1) is
Low, Output Enable (G) is Low, Upper Byte En-
able (UB) and/or Lower Byte Enable (LB) is Low),
then Write Enable (W) will return the outputs to
high impedance within t
Care must be taken to avoid bus contention in this
type of operation. Data input must be valid for t
VWH
for t
(E1), whichever occurs first, and remain valid for
t
See Figures 13, 14, 15, 16,
12., Write Mode AC
8/29
WHDZ
and
BLQV
Waveforms):
–
–
–
–
–
–
–
–
DVEH
before the rising edge of Write Enable (W), or
, t
Operating Modes
ELQX
Table 11., Read Mode AC
BHDZ or
Apply power and wait for V
Wait 300µs while driving both Chip Enable
signals (E1 and E2) High
Write Enable (W) is High and
Output Enable (G) is Low and
the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
Write Enable (W) is Low and
at least one of Upper Byte Enable (UB)
and Lower Byte Enable (LB) is Low
the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
) depends on which of the above signals
before the rising edge of Chip Enable
, t
GLQX
t
AVQV
EHDZ
AVWL
and t
. See Figures 8, 9, 10,
Characteristics, for details of
.
Figure 25., Power-Up Mode
or t
table (see Table 2).
BLQX
WHDZ
AVEL
17
, but data will always
or t
of its rising edge.
and 18, and
Characteristics,
AVBL
CC
ELQV
to stabilize
).
, t
11
Table
GLQV
and
D-
the timing requirements. Figures 19, 20,
show Read and Write mode AC waveforms.
Standby Mode
The device is in Standby mode when:
The input/output buffers and the decoding/control
logic are switched off, but the dynamic array con-
tinues to be refreshed. In this mode, the memory
current consumption, I
remains valid.
See
forms, After Read
AC Characteristics
Power-Down Modes
Description. The M69AR048B has four Power-
down modes, Deep Power-down, 4Mbit Partial
Power-Down, 8Mbit Partial Power-Down, and
16Mbit Partial Power-Down (see Table 3).
These can be entered using a series of read and
write operations. Each mode has the following fea-
tures. The default state is Deep Power-Down and
it is the lowest power consumption but all data will
be lost once E2 is brought Low for Power-down.
No sequence is required to put the device in Deep
Power-down mode after Power-up.
The device is in one of the Power-Down modes
when:
All the device logic is switched off and all internal
operations are suspended. This gives the lowest
power consumption. In this operating mode, no re-
fresh is performed, and data is lost if the duration
is longer than 10ns. This mode is useful for those
applications where the data contents are no longer
needed, and can be lost, but where reduced cur-
rent consumption is of major importance.
See
forms
teristics
Power-Down Program Sequence. The Power-
Down Program sequence is used to program the
Power-Down Configuration. It requires a total of six
read and write operations, with specific addresses
and data. Between each read or write operation
the device must be in Standby mode.
Table 4 and
first cycle, the Byte at the highest memory address
(MSB) is read. In the second and third cycles, the
data (RDa) read by first cycle are written back. If
the third cycle is written into a different address, the
sequence is aborted, and the data written by the
third cycle is valid as in a normal write operation. In
the fourth and fifth cycles, the Power-Down Config-
–
–
–
Figure 26., Standby Mode Entry AC Wave-
Figure 24., Power-Down Mode AC Wave-
and
Chip Enable (E1) is High and
Chip Enable (E2) is High
Chip Enable (E2) is Low
for details.
Table 13., Standby Mode AC Charac-
Figure 23.
and
for details.
SB
show the sequence. In the
Table 13., Standby Mode
, is reduced, and the data
21
and
22