mt8lsdt3264ay-13e Micron Semiconductor Products, mt8lsdt3264ay-13e Datasheet - Page 13

• Manufacturer Part Number: mt8lsdt3264ay-13e
• Description: 256mb X64, Sr , 512mb X64, Dr 168-pin Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Write Burst Mode
Table 8:
Commands
Table 9:
PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
CAS Latency Table
Truth Table – SDRAM Commands and DQMB Operation
CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table
Notes: 1. A0–A12 provide row address; BA0–BA1 determine which device bank is made active.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
When M9 = 0, the burst length programmed via M0–M2 applies to both READ and
WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
The Truth Table provides a quick reference of available commands. This is followed by
written description of each command. For a more detailed descrip-tion of commands
and operations, refer to the 256Mb SDRAM component data sheet.
2. A0–A9 provide column address; A10 HIGH enables the auto-precharge feature (nonpersis-
3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
tent), while A10 LOW disables the auto-precharge feature; BA0-BA1 determine which
device bank is being read from or written to.
device banks are precharged and BA0, BA1 are “Don’t Care.”
except for CKE.
delay).
Speed
-13E
-133
-10E
256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
CS#
H
L
L
L
L
L
L
L
L
–
–
13
CAS Latency = 2
Allowable Operating Clock Frequency (MHz)
RAS# CAS# WE# DQMB
≤ 133
≤ 100
≤ 100
X
H
H
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
L
L
L
L
–
–
X
H
H
H
H
L
L
L
L
–
–
L/H
L/H
H
X
X
X
X
X
X
X
L
Bank/Row
©2003 Micron Technology, Inc. All rights reserved.
Bank/Col
Bank/Col
CAS Latency = 3
Op-code
ADDR
Code
X
X
X
X
–
–
≤ 143
≤ 133
NA
High-Z
Active
Active
Commands
Valid
DQ
X
X
X
X
X
X
X
Notes
4, 5
1
2
2
3
6
7
7