mt18htf25672fy-667 Micron Semiconductor Products, mt18htf25672fy-667 Datasheet - Page 9

• Manufacturer Part Number: mt18htf25672fy-667
• Description: 1gb, 2gb X72, Sr 240-pin Ddr2 Sdram Fbdimm
• Manufacturer: Micron Semiconductor Products

I
Table 10:
Table 11:
Table 12:
Table 13:
pdf: 09005aef81a2f214/source: 09005aef81a2f22d
HTF18C64_128_256x72F.fm - Rev. B 9/07 EN
Symbol
I
I
I
I
I
I
I
I
I
Total power
I
I
Total power
I
I
Total power
DD
DD
DD
DD
DD
DD
DD
DD
CC
DD
CC
DD
CC
DD
_Idle_0
_Idle_1
_Active_1
_Active_2
_Training
_IBIST
_EI
Symbol
Symbol
Symbol
Conditions and Specifications
I
I
I
I
DD
DD
DD
DD
Conditions
Specifications – 1GB DDR2-533
Specifications – 1GB DDR2-667
Specifications – 1GB DDR2-800
I
I
I
Notes:
Notes:
DD
DD
DD
2,200
1,620
2,600
1,710
_Idle_0
_Idle_0
_Idle_0
TBD
TBD
TBD
6.5
7.3
1. Actual test conditions may vary from published JEDEC test conditions.
1. Total power is based on maximum voltage levels, I
Condition
Idle current, single, or last DIMM: L0 state; Idle (0 percent bandwidth); Primary channel
enabled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2
SDRAM clock active
Idle current, first DIMM: L0 state; Idle (0 percent bandwidth); Primary and secondary
channels enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active
Active power: L0 state; 50 percent DRAM bandwidth; 67 percent READ; 33 percent WRITE;
Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH
Active power, data pass through: L0 state; 50 percent DRAM bandwidth to downstream
DIMM; 67 percent READ; 33 percent WRITE; Primary and secondary channels enabled; DDR2
SDRAM clock active; CKE HIGH; Command and address lines stable
Training: Primary and secondary channels enabled; 100 percent toggle on all channel lanes;
DRAMs idle; 0 percent bandwidth; CKE HIGH; Command and address lines stable; DDR2
SDRAM clock active
IBIST over all IBIST modes: DRAM idle (0 percent bandwidth); Primary channel enabled;
Secondary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM
clock active
Electrical idle: DRAM idle (0 percent bandwidth); Primary channel disabled; Secondary
channel disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active;
ODT and CKE driven LOW
I
I
I
DD
DD
DD
3,000
1,620
3,400
1,710
_Idle_1 I
_Idle_1 I
_Idle_1 I
TBD
TBD
TBD
7.8
8.6
DD
DD
DD
_Active_1 I
_Active_1 I
_Active_1 I
3,400
3,470
3,900
3,845
11.9
13.4
TBD
TBD
TBD
1GB, 2GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
9
DD
DD
DD
_Active_2 I
_Active_2 I
_Active_2 I
3,200
1,620
3,700
1,710
TBD
TBD
TBD
8.1
9.0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
DD
DD
DD
DD
_Training
_Training
_Training
Conditions and Specifications
3,500
1,620
4,000
1,710
CC
TBD
TBD
TBD
8.6
9.5
@ 1.575V and I
I
I
I
DD
DD
DD
©2005 Micron Technology, Inc. All rights reserved.
3,800
1,620
4,500
1,710
10.3
TBD
TBD
TBD
_IBIST
9.0
_IBIST
_IBIST
DD
@ 1.9V.
I
I
I
2,000
DD
2,500
DD
DD
326
TBD
TBD
TBD
3.8
326
4.6
_EI
_EI
_EI
Units
Units
Units
mA
mA
mA
mA
mA
mA
W
W
W