mt18vddt12872ag-40b Micron Semiconductor Products, mt18vddt12872ag-40b Datasheet - Page 12

• Manufacturer Part Number: mt18vddt12872ag-40b
• Description: 256mb, 512mb, 1gb, 2gb X72, Ecc, Dr 184-pin Ddr Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 14:
PDF: 09005aef80814e61/Source: 09005aef807f8acb
DD18C32_64_128_256x72A.fm - Rev. C 10/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
cycle
Precharge power-down standby current: All device banks idle; Power-down
mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-down
mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank; Active
precharge;
twice per clock cycle; Address and other control inputs changing once per clock
cycle
Operating burst read current: BL = 2; Continuous burst reads; One device bank
active; Address and control inputs changing once per clock cycle;
I
Operating burst write current: BL = 2; Continuous burst writes; One device
bank active; Address and control inputs changing once per clock cycle;
t
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving reads;
BL = 4 with auto precharge;
inputs change only during active READ or WRITE commands
CK =
CK =
OUT
CK =
IN
= V
= 0mA
t
t
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
REF
t
t
CK =
CK =
for DQ, DQS, and DM
t
RC =
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
I
Values are shown for the MT46V128M8 DDR SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
DD
t
OUT
RAS (MAX);
Specifications and Conditions – 2GB
Notes:
= 0mA; Address and control inputs changing once per clock
t
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
RC =
t
CK =
in I
t
256MB, 512MB, 1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM
DD
RC (MIN);
t
CK (MIN); DQ, DM, and DQS inputs changing
2P (CKE LOW) mode.
t
CK =
t
CK (MIN); Address and control
t
RC =
t
RC (MIN);
t
t
t
CK =
REFC =
REFC = 7.8125µs
12
t
t
CK (MIN);
RC =
t
CK =
t
RFC (MIN)
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RC (MIN);
t
CK (MIN);
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
2F
3P
4R
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
Electrical Specifications
1
©2004 Micron Technology, Inc. All rights reserved.
1,530
1,185
1,710
2,070
2,160
6,120
4,815
-335
180
630
900
180
162
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA