mt18vddt12872dg-265 Micron Semiconductor Products, mt18vddt12872dg-265 Datasheet - Page 11

• Manufacturer Part Number: mt18vddt12872dg-265
• Description: 256mb, 512mb, 1gb, 2gb X72, Ecc, Dr 184-pin Ddr Rdimm
• Manufacturer: Micron Semiconductor Products

Table 12:
PDF: 09005aef80e1141d/Source: 09005aef80e11353
DD18C32_64_128_256x72D.fm - Rev. D 4/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock
cycle; V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle;
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank
interleaving reads (BL = 4) with auto precharge;
(MIN); Address and control inputs change only during active READ or
WRITE commands
CK =
RC =
t
t
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
CK =
CK =
t
IN
RC =
= V
t
t
REF
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
t
t
RAS (MAX);
I
Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
CK =
CK =
DD
for DQ, DM, and DQS
t
CK =
Specifications and Conditions – 512MB
Notes:
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
t
CK (MIN); I
OUT
t
CK =
= 0mA
1. Value calculated as one module rank in this operating condition; all other module ranks in
2. Value calculated reflects all module ranks in this operating condition.
I
t
DD
CK (MIN); DQ, DM, and DQS inputs
OUT
2P (CKE LOW) mode.
256MB, 512MB, 1GB, 2GB (x72, ECC, DR) 184-Pin DDR RDIMM
= 0mA; Address and control inputs
t
RC =
t
RC =
t
t
t
REFC =
REFC = 7.8125µs
RC (MIN);
t
t
RC (MIN);
CK =
11
t
RFC (MIN)
t
CK (MIN);
t
CK =
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CK
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
1
1,161
1,566
1,080
1,611
1,611
4,590
3,726
-335
900
540
108
72
72
Electrical Specifications
1,161
1,476
1,386
1,386
4,230
3,186
-262
810
450
900
108
72
72
©2003 Micron Technology, Inc. All rights reserved
-26A/
1,116
1,341
1,386
1,386
4,230
3,186
-265
810
450
900
108
72
72
1,116
1,341
1,386
1,386
4,410
3,321
-202
810
540
900
108
72
72
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA