mt18lsdt12872a Micron Semiconductor Products, mt18lsdt12872a Datasheet - Page 19

• Manufacturer Part Number: mt18lsdt12872a
• Description: Synchronous Dram Module
• Manufacturer: Micron Semiconductor Products

Notes
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no more than once every two clocks and
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
22. V
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured at 1.5V with equivalent load:
1.4V; f = 1 MHz.
with minimum cycle time and the outputs open.
operation over the full temperature range is ensured.
commands, before proper device operation is ensured. (V
ered up simultaneously. V
REFRESH command wake-ups should be repeated any time the
ment is exceeded.
sit between V
t
a reference to V
High-Z.
crossover point. If the input transition time is longer than 1ns, then the timing is ref-
erenced at V
are otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
frequency alteration for the test condition.
cannot be greater than one third of the cycle rate. V
a pulse width ≤ 3ns for all inputs except A12. V
V
third of the cycle rate.
DD
Q
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
IH
DD
is dependent on output loading and cycle rates. Specified values are obtained
specifications are tested after the device is properly initialized.
overshoot: V
Q + 1V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one
DD
current will increase or decrease proportionally according to the amount of
t
CK = 7.5ns for -133 and -13E.
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
IL
IH
50pF
(MAX) and V
OH
DD
and V
IH
or V
tests have V
(MAX) = V
IL
OL
IH
(or between V
. The last valid data element will meet
SS
or V
t
19
SS
T = 1ns.
IH
and V
t
t
t
.
DD
CKS; clock(s) specified as a reference only at minimum
WR plus
WR.
DD
(MIN) and no longer at the ISV crossover point.
IL
IL
, V
Q + 2V for a pulse width ≤ 3ns, and the pulse width
levels.
= 0V and V
SS
DD
Q must be at same potential.) The two AUTO
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q = +3.3V; T
IL
t
RP; clock(s) specified as a reference only at
and V
IH
IH
= 3.0V, with timing referenced to 1.5V
IH
) in a monotonic manner.
overshoot for pin A12 is limited to
A
= 25°C; pin under test biased at
IL
undershoot: V
DD
©2002 Micron Technology, Inc. All rights reserved.
and V
t
OH before going
t
REF refresh require-
DD
IL
Q must be pow-
(MIN) = -2V for
Notes