mt18lsdt12872a Micron Semiconductor Products, mt18lsdt12872a Datasheet - Page 9

• Manufacturer Part Number: mt18lsdt12872a
• Description: Synchronous Dram Module
• Manufacturer: Micron Semiconductor Products

Mode Register Definition
Burst Length
Burst Type
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All device
banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length, a burst type, a CAS latency, an operat-
ing mode and a write burst mode, as shown in Figure 5 on page 10. The mode register is
programmed via the LOAD MODE REGISTER command and will retain the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefined but should be driven LOW during loading of the
mode register.
The mode register must be loaded when all device banks are idle, and the controller
must wait the specified time before initiating the subsequent operation. Violating either
of these requirements will result in unspecified operation.
Read and write accesses to the SDRAM are burst oriented, with the burst length being
programmable, as shown in Figure 5 on page 10. The burst length determines the maxi-
mum number of column locations that can be accessed for a given READ or WRITE
command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and
the interleaved burst types, and a full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST TERMINATE command to gener-
ate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached, as shown in
the Table 6 on page 11. The block is uniquely selected by A1– A9, A11 when BL = 2;
A2–A9, A11 when BL = 4; and by A3–A9, A11 when BL = 8. The remaining (least signifi-
cant) address bit(s) is (are) used to select the starting location within the block.
Full-page bursts wrap within the page if the boundary is reached, as shown in Table 6 on
page 11.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address, as shown in Table 6 on page 11.
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
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Mode Register Definition
©2002 Micron Technology, Inc. All rights reserved.