mt9htf12872pz Micron Semiconductor Products, mt9htf12872pz Datasheet - Page 10

• Manufacturer Part Number: mt9htf12872pz
• Description: 1gb X72, Ecc, Sr 240-pin Ddr2 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

I
Table 8:
PDF: 09005aef83c641c6/Source: 09005aef83c6415f
HTF9C128x72pz.fm - Rev. A 11/09 EN
Parameter/Condition
Operating one bank active-precharge current:
t
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
t
inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst reads,
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads,
I
t
between valid commands; Address bus inputs are stable during deselects; Data
bus inputs are switching
DD
OUT
OUT
RAS =
RCD =
CK =
RP =
RC =
Specifications
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
t
t
RP (I
RC (I
CK (I
DD
t
t
RAS MIN (I
RCD (I
),
DD
DD
DD
t
RP =
); CKE is HIGH, S# is HIGH between valid commands; Address bus
),
DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
); CKE is LOW; Other control and address bus
DD
t
DD
RRD =
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
t
RP (I
DD
), AL = 0;
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address
DD
DD
t
RRD (I
t
); CKE is HIGH, S# is HIGH between valid commands;
CK =
Specifications and Conditions – 1GB
t
t
CK =
CK =
DD
DD
DD
t
CK (I
), AL =
), AL = 0;
),
t
t
t
CK (I
CK (I
RCD =
DD
); REFRESH command at every
t
DD
RCD (I
DD
t
),
t
CK =
),
RCD (I
t
t
RAS =
RC =
DD
DD4W
t
CK (I
) - 1 ×
DD
t
t
RC (I
t
CK =
); CKE is HIGH, S# is HIGH
RAS MAX (I
t
CK =
DD
t
CK =
t
DD
),
CK (I
1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
t
CK (I
t
t
),
RAS =
CK (I
t
OUT
CK =
t
t
t
CK (I
DD
RAS =
CK =
10
DD
);
= 0mA;
DD
DD
t
),
DD
t
t
CK (I
RAS MAX (I
CK =
),
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
),
CK (I
t
t
); CKE is HIGH,
RAS =
t
RAS MIN (I
t
RC =
RP =
t
DD
RFC (I
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
CK (I
); CKE is
t
t
t
); CKE is
RC (I
RP (I
RAS
DD
DD
DD
DD
DD
DD
)
),
),
),
);
),
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
DD7
Electrical Specifications
-80E/
-800
1440
1440
2115
3015
©2009 Micron Technology, Inc. All rights reserved.
810
990
450
450
360
540
63
90
63
-667
1215
1215
1935
2520
765
900
360
360
270
495
63
90
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA