m368l1624dtm Samsung Semiconductor, Inc., m368l1624dtm Datasheet
m368l1624dtm
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m368l1624dtm Summary of contents
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... Unbuffered DIMM DDR SDRAM Unbuffered Module (DDR400 Module) 184pin Unbuffered Module based on 256Mb D-die 64/72-bit Non ECC/ECC Revision 1.2 May. 2003 DDR SDRAM Rev. 1.2 May. 2003 ...
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Unbuffered DIMM Revision History Revison 0.0 (June. 2002) 1. First release Revison 0.1 (Aug. 2002) - Changed IDD3P value from 40mA to 55m - Changed IDD3N value from 60mA to 75mA Revision 1.0 (February, 2003) - Modified ...
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... Unbuffered DIMM 184Pin Unbuffered DIMM based on 256Mb D-die (x8, x16) Ordering Information Part Number M368L1624DTM-C(L)CC/C4 M368L3223DTM-C(L)CC/C4 M368L6423DTM-C(L)CC/C4 M381L3223DTM-C(L)CC/C4 M381L6423DTM-C(L)CC/C4 Operating Frequencies Speed @CL3 CL-tRCD-tRP Feature • Power supply : Vdd: 2.6V ± 0.1V, Vddq: 2.6V ± 0.1V • Double-data-rate architecture; two data transfers per clock cycle • ...
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... These pins are not used in this module. 2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module, and are not used on x64 module. 3. Pins 111, 158 are NC for 1 Row Module[M368L1624DTM, M368(81)L3223DTM] & used for 2 Row Moduel[M368(81)L6423DTM] Pin Description ...
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... Unbuffered DIMM 128MB, 16M x 64 Non ECC Module (M368L1624DTM) Functional Block Diagram CS0 DQS1 LDQS CS DM1 LDM DQ8 I/O 6 DQ9 I DQ10 I/O 1 DQ11 I/O 3 DQ12 I/O 2 DQ13 I/O 0 DQ14 I/O 5 DQ15 I/O 7 DQS0 UDQS DM0 UDM DQ0 I/O 8 DQ1 I/O 10 DQ2 I/O 15 DQ3 I/O 13 DQ4 I/O 12 DQ5 I/O 14 DQ6 I/O 11 DQ7 ...
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... BA0-BA1 : DDR SDRAMs A12 A0-A12 : DDR SDRAMs RAS RAS : DDR SDRAMs CAS CAS : DDR SDRAMs CKE0 CKE : DDR SDRAMs DDR SDRAMs (Populated as 1 bank of x8 DDR SDRAM Module) DQS4 DM4 DM CS DQS DQ32 I/O 7 DQ33 I ...
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... BA0-BA1 : DDR SDRAMs A12 A0-A12 : DDR SDRAMs RAS RAS : DDR SDRAMs CAS CAS : DDR SDRAMs CKE0 CKE : DDR SDRAMs DDR SDRAMs (Populated as 1 bank of x8 DDR SDRAM Module) DQS4 DM4 DM CS DQS DQ32 I/O 7 DQ33 I ...
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... CKE : DDR SDRAMs D8 - D15 CKE0 CKE : DDR SDRAMs DDR SDRAMs D0 - D15 V DDSPD SPD DDQ D0 - D15 D0 - D15 VREF D0 - D15 D15 SS (Populated as 2 bank of x8 DDR SDRAM Module) CS1 DQS4 DM4 DQS DM CS DQS DQ32 I/O 0 DQ33 I DQ34 I/O 6 DQ35 I/O 7 DQ36 I/O 2 ...
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... CAS : DDR SDRAMs D0 - D17 CKE1 CKE : DDR SDRAMs D9 - D17 CKE0 CKE : DDR SDRAMs DDR SDRAMs D0 - D17 V DDSPD DDQ VREF V SS (Populated as 2 bank of x8 DDR SDRAM Module) CS1 DQS4 DM4 DQS DM CS DQS DQ32 I/O 0 DQ33 I DQ34 I/O 6 DQ35 ...
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Unbuffered DIMM Absolute Maximum Ratings Parameter Voltage on any pin relative to V Voltage on V & V supply relative DDQ Storage temperature Power dissipation Short circuit current Note : Permanent device damage may ...
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... Unbuffered DIMM DDR SDRAM IDD spec table M368L1624DTM(Non ECC) Symbol CC(DDR400@CL=3) C4(DDR400@CL=3) CC(DDR400@CL=3) C4(DDR400@CL=3) IDD0 440 IDD1 600 IDD2P 16 IDD2F 120 IDD2Q 100 IDD3P 220 IDD3N 300 IDD4R 880 IDD4W 1000 IDD5 800 IDD6 Normal 12 Low power 6 IDD7A 520 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap ...
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Unbuffered DIMM DDR SDRAM IDD spec table Symbol CC(DDR400@CL=3) IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A M381L6423DTM(ECC) C4(DDR400@CL=3) 1620 1850 75 540 450 990 1350 2340 2660 2480 54 ...
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... DC level of the same. DDQ V =0.5*V tt DDQ R =50: T Z0=50: V REF =0.5*V DDQ C =30pF LOAD Output Load Circuit (SSTL_2) M368L1624DTM M368L3223DTM M381L3223DTM Symbol Min Max CIN1 41 45 CIN2 34 38 CIN3 34 38 CIN4 25 30 CIN5 6 7 Cout1 ...
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Unbuffered DIMM AC Timing Parameters and Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Internal write to ...
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Unbuffered DIMM Parameter Data hold skew factor Auto Precharge write recovery + precharge time Exit self refresh to non-READ command Exit self refresh to READ command Component Notes 1.V is the magnitude of the difference between the ...
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Unbuffered DIMM System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR400 devices to ensure proper system perfor- mance. these characteristics are for system simulation purposes and are guaranteed by design. Table ...
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Unbuffered DIMM System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1. Output Figure 1 : Pullup slew rate test load b. Pulldown slew rate is measured under the ...
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Unbuffered DIMM j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of ...
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Unbuffered DIMM Command Truth Table COMMAND Register Extended MRS Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & ...
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... Unbuffered DIMM Physical Dimensions : 16M x 64 (M368L1624DTM) PACKAGE DIMENSIONS 1.25 r (31.75 r 0.250 (6.350) 0.26 (6.62) 2.175 0.071 Detail A Tolerances : ± 0.005(.13) unless otherwise specified. The used device is 16Mx16 DDR SDRAM, TSOP. DDR SDRAM Part NO : K4H561638D 5.25 ± 0.005 (133.350 ± 0.13) 5.077 (128.950 ...
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Unbuffered DIMM Physical Dimensions : 32M x 64 (M368L3223DTM), 32M x 72 (M381L3223DTM) PACKAGE DIMENSIONS 1.25 r (31.75 r 0.250 (6.350) 0.26 (6.62) 2.175 Detail A Tolerances : ± 0.005(.13) unless otherwise specified. The used device is ...
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Unbuffered DIMM Physical Dimensions : 64M x 64 (M368L6423DTM), 64M x 72 (M381L6423DTM) PACKAGE DIMENSIONS 1.25 r (31.75 r 0.250 (6.350) 0.26 (6.62) 2.175 Detail A Tolerances : ± 0.005(.13) unless otherwise specified. The used device is ...