m368l1624dtm Samsung Semiconductor, Inc., m368l1624dtm Datasheet - Page 14

• Manufacturer Part Number: m368l1624dtm
• Description: 184pin Unbuffered Module Based On 256mb D-die 64/72-bit Non Ecc/ecc
• Manufacturer: Samsung Semiconductor, Inc.

128MB, 256MB, 512MB Unbuffered DIMM
AC Timing Parameters and Specifications
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Internal write to read command delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
Write preamble setup time
Write preamble
Write postamble
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time
Address and Control Input hold time
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS, slew rate 0.5V/ns
DQ & DM hold time to DQS, slew rate 0.5V/ns
DQ & DM input pulse width
Control & Address input pulse width for each input
Refresh interval time
Output DQS valid window
Clock half period
Parameter
Up to 128Mb
256Mb, 512Mb, 1Gb
CL=3.0
CL=2.5
tWPRES
tDQSCK
Symbol
tDQSQ
tWPRE
tRPRE
tDQSS
tWPST
tDQSH
tRPST
tDQSL
tDIPW
tRCD
tWTR
tMRD
tREFI
tRFC
tRAS
tRRD
tDSS
tDSH
tIPW
tWR
tCK
tDH
tQH
tRC
tRP
tCH
tAC
tDS
tHP
tCL
tHZ
tLZ
tIS
tIH
- CC(DDR400@CL=3)
tAC min
tCH/tCL
-tQHS
-0.55
-0.65
0.45
0.45
0.72
0.25
0.35
0.35
1.75
15.6
Min
tHP
min
0.9
0.4
0.4
0.2
0.2
0.6
0.6
0.4
0.4
2.2
7.8
55
70
40
15
15
10
15
2
5
6
0
2
-
-
tAC max
tAC max
+0.55
+0.65
Max
0.55
0.55
70K
1.28
0.4
1.1
0.6
0.6
10
12
-
-
- C4(DDR400@CL=3)
tAC min
tCH/tCL
-tQHS
-0.55
-0.65
0.45
0.45
0.72
0.25
0.35
0.35
1.75
15.6
Min
tHP
min
0.9
0.4
0.4
0.2
0.6
0.4
0.4
2.2
0.2
0.6
7.8
70
40
18
18
15
60
10
2
5
6
0
2
-
-
Rev. 1.2 May. 2003
tAC max
tAC max
+0.55
+0.65
Max
0.55
0.55
1.28
70K
0.4
1.1
0.6
0.6
10
12
-
-
DDR SDRAM
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
us
us
ns
ns
h,7~10
h,7~10
11, 12
Note
16
13
12
i, j
i, j
5
4
3
3
9
9
6